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AR# 67629

SMPTE SD/HD/3G-SDI v3.0 - XAPP1290 - When using the XAPP1290 reference design, I cannot see the Color Bar when using CPLL

Description

After I change the GT type to CPLL when using the XAPP1290 reference design, I cannot see the Color Bar. 

How can I fix this problem?

Solution

For the UltraScale+ GTH/GTY CPLL, the CPLL calibration block should be used to ensure that the CPLL locks reliably and acquires the correct frequency.

This calibration block is not generated in the GT wizard by default. This will be enabled automatically by the Wizard from Vivado 2016.3 on.

For versions prior to 2016.3, You will need to enable it manually by setting C_INCLUDE_CPLL_CAL to 1:

create_property C_INCLUDE_CPLL_CAL cell -type int
set_property C_INCLUDE_CPLL_CAL 1 [get_cells {*/genblk1[0].sdi_wrapper_support/sdi_wrapper/smpte_3gsdi_gtwiz_i/inst}]

For more details on this issue, please refer to (Xilinx Answer 67320)

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
67320 Kintex/Virtex/Zynq UltraScale+ MPSoC: Incorrect GTH/GTY CPLL Frequency N/A N/A
AR# 67629
Date Created 08/02/2016
Last Updated 08/16/2016
Status Active
Type General Article
IP
  • SMPTE SD/HD/3G-SDI