The example design simulation can take several hours to complete. Is there a way to speed up the simulation?
Simulations involving the complex transceiver models can take long periods of time to complete.
If your simulation involves the 40G/50G Ethernet Sub-System operating in a loopback scenario, an additional method to improve simulation time is to reduce the PCS lane Alignment Marker (AM) spacing in order to speed up the time the IP will take to achieve PCS Lane lock.
This can be acheived by changing CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from the default of 16'h3FFF to 16'h03FF.