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AR# 67712

UltraScale+ PCI Express Integrated Block (Vivado 2016.2) - Failed to generate IP 'pcie4_uscale_plus_0'. Failed to generate 'Any Language Examples' outputs:

Description

Version Found: v1.1 Rev1 (Vivado 2016.2)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

When generating the UltraScale+ PCI Express Integrated Block core for xcvu9p-flgc2104 and xcvu9p-flga2577 with non-default GT locations, the tools gives the following error message when opening the example design:

Failed to generate IP 'pcie4_uscale_plus_0'. Failed to generate 'Any Language Examples' outputs:


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This is a known issue and will be fixed in a future release of the core. For Vivado 2016.2, please install the tactical patch attached as described below:

METHOD 1:

  1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
  2. Extract the contents of the ".zip" archive to a directory starting with the name AR67712
    Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
  3. Run Vivado software tools from the original install location.


METHOD 2:

  1. Create a separate directory for the patched files
  2. Extract the contents of the ".zip" archive to the desired patch directory location
  3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
    For example:
    set MYVIVADO=C:\MYVIVADO\vivado-patch-AR67712\vivado\
  4. Run Vivado software tools from the original install location.


Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions. This is an issues with latency of the core.

Revision History:

08/16/2016 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR67712_Vivado_2016_2_preliminary_rev1.zip 799 KB ZIP
AR# 67712
Date Created 08/11/2016
Last Updated 11/01/2016
Status Active
Type Known Issues
IP
  • UltraScale+ FPGA Integrated Endpoint Block for PCI Express