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AR# 67715

UltraScale: BSDL Compliance with PUDC_B


According to the User Guide, for compliance with the pre-configuration BSDL file description, PUDC_B should be set to 1.

In the actual BSDL files, I only see the PROGRAM_B compliance:

-- Compliance-Enable Description

attribute COMPLIANCE_PATTERNS of XCVU095_FFVD1924 : entity is

        "(PROGRAM_B) (1)";

So is this truly a compliance issue? What are the implications if PUDC_B is not tied to 1?


There are no practical ramifications if you do not match the PUDC_B setting to the BSDL disable result description.

The specific affected BSDL compliance feature allows a boundary-scan tool to theoretically create a boundary-scan test for an internal pull-up in the Xilinx device only when PUDC_B is enabled. However, internal pull-ups are already well covered by Xilinx device testing so there is no value added by the boundary-scan tool internal pull-up test.


The feature in question is related to the expected value of a board signal trace when no output is driving the signal during a boundary-scan test.

The boundary-scan tools can read from a device BSDL file that an output to the signal trace has an internal pull-up (or pull-down), and if an internal pull-up (or pull-down) is present, can disable all outputs to the signal trace and theoretically test for the presence of the internal pull-up (or pull-down). 

Our pre-configuration BSDL file says the disable result value is Z (NO internal pull-up and NO internal pull-down) so the boundary-scan tools think there is NO internal pull-up or pull-down to test. As a result no such test is created for the device pin, so there is no test that would fail for any setting of PUDC_B.

AR# 67715
Date 08/29/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
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