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AR# 67728

10G/25G Ethernet SubSystem - 2016.1/2016.2 - I have an Asynchronous System how can I use the same clock for the RX and TX AXI or MII interface

Description

I am using the 10G/25G Ethernet Subsystem. In the 2016.1 and 2016.2 releases, the RX and TX AXI or MII interface is driven by the GT RX USERCLK2.

If I have an asynchronous system (up to per spec total +/-200ppm difference between the reference clocks on each side of the serial link), can I use the same clock to drive the RX and TX AXI or MII interface?

Solution

Yes, this is possible in either the MAC+PCS/PMA configuration or the PCS/PMA only configuration.  

If using PCS/PMA only an RX FIFO is always used. If using MAC+PCS/PMA the RX FIFO can be selected.  The following steps should be followed:

1) When Generating the core under the "Configuration" table for Clocking, select: "Asynchronous" to indicate that refclks on either side of link are asynchronous.

2) If using MAC, under the "MAC Options" tab, check the "Include FIFO Logic" option.

3) Open the core_name_wrapper.v file in an external text editor.

If using the PCS/PMA only option for each lane, change the following text:

 .rx_mii_clk (gt_rxusrclk2_0),

   ...

.rx_mii_clk (gt_rxusrclk2_3),

Change the text to:

 .rx_mii_clk (gt_txusrclk2_0),

   ...

.rx_mii_clk (gt_txusrclk2_3),


If using the MAC+PCS/PMA only option for each lane (user can select to have 1 to 4 lanes), change the following text:

.rx_clk (gt_rxusrclk2_0),

    ..

.

.rx_clk(gt_rxuserclk2_3),

Change the text to:

  .rx_clk (gt_txusrclk2_0),

    ..

.

  .rx_clk(gt_txuserclk2_3),


4) Re-run out-of-context Synthesis for the core (if used) and Synthesis for the whole design.


In the 2016.3 release and later, users will have access at the XCI level of the core to drive the RX MII and RX AXI clock input.

AR# 67728
Date Created 08/16/2016
Last Updated 08/26/2016
Status Active
Type General Article
IP
  • Ethernet