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AR# 67740

Zynq UltraScale+ MPSoC: XSDB (or any other JTAG user) needs to hold TMS signal high for 5 TCK cycles to enable PL TAP linking to the JTAG chain.


Zynq UltraScale+ devices with silicon revision versions higher than 1.0 will require TMS to be asserted high for 5 TCK cycles.

This requirement is added to guarantee that the PS TAP, PL TAP and DAP state machines are synchronized after linking.

The TMS signal needs to be asserted high for an additional 5 cycles after Update-DR state.

Here is the sequence that needs to be implemented:

  1. Shift JTAG_CTRL instruction into the PS_TAP
  2. Go to Shift-DR state and shift in the new JTAG configuration
  3. Go to Update-DR state
    • Link value is updated in JTAG_CTRL register
    • TMS/TCK to the PL_TAP/DAP is now linked to allow the TMS to be applied for 5x TCK cycles
  1. Hold TMS high for 5 cycles of TCK
    • The new delayed LINK value is updated
    • TDI/TDO to/from the PL_TAP/DAP are now linked to the JTAG

The 2016.2 release of XSDB does not guarantee those 5 TCK cycles after a "rst -srst" command.

As a result, roughly 5% of the time, the PL TAP is not visible on the JTAG chain after a "rst -srst" (jtag_chain_status = 0x2).


The work-around in 2016.2 XSDB is to perform the following sequence every time a "rst -srst" is executed:

rst -srst

exec sleep.exe 1

set value [mrd -force 0xFFCA0034]

if { $value == 2} {

mwr -force 0xFFCA0030 0x1


It is planned to update XSDB in future releases so that this requirement is transparent to XSDB users.

AR# 67740
Date Created 08/18/2016
Last Updated 08/31/2016
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2016.2