Zynq UltraScale+ devices with silicon revision versions higher than 1.0 will require TMS to be asserted high for 5 TCK cycles.
This requirement is added to guarantee that the PS TAP, PL TAP and DAP state machines are synchronized after linking.
The TMS signal needs to be asserted high for an additional 5 cycles after Update-DR state.
Here is the sequence that needs to be implemented:
The 2016.2 release of XSDB does not guarantee those 5 TCK cycles after a "rst -srst" command.
As a result, roughly 5% of the time, the PL TAP is not visible on the JTAG chain after a "rst -srst" (jtag_chain_status = 0x2).
The work-around in 2016.2 XSDB is to perform the following sequence every time a "rst -srst" is executed:
It is planned to update XSDB in future releases so that this requirement is transparent to XSDB users.