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AR# 67756

2016.2 Vivado HLS - CRITICAL WARNING: [RTGEN 206-102] Illegal connection is found on FIFO pin 'top|ovflo' connecting to 'stg_356'('top_fft_top|ovflo').

Description

I see the following error in C synthesis in Vivado HLS:

CRITICAL WARNING: [RTGEN 206-102] Illegal connection is found on FIFO pin 'top|ovflo' connecting to 'stg_356'('top_fft_top|ovflo').
CRITICAL WARNING: [HLS 200-103] RTL generation terminated by exceptions!
Synthesis failed.

How do I resolve this issue?

Solution

This issue can be seen when an interface directive is added in the sub module when the signal is not connected to the top interface.

For example:

top (){
    bool ovflo;
    fft_top(1, in, out, &ovflo);
}

void fft_top(
bool direction, DataInType in[512], DataOutType out[512],bool* ovflo) {
......
#pragma HLS interface ap_fifo depth=1 port=ovflo
......
}

To resolve this issue, delete the unnecessary interface directive in the sub module.

AR# 67756
Date Created 08/23/2016
Last Updated 08/31/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite