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AR# 67850

2018.2 Vivado IP Flows - Validating an IP Integrator block design gives ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified


I have a project with an IP Integrator Block Design (BD) which has two instances of the IP "ocl_block".

When running synthesis for this project, The out of context (OOC) synthesis issues the following error:

ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified


The issue is that 'launch_runs' does not recursively generate all composite files in the BD hierarchy when the "validate_bd_design -force" command is used.

To work around this, run 'generate_target synthesis' for the BD before issuing the 'launch_runs' command.

This will properly analyze the hierarchy and generate all of the expected composite files.

So, the following commands must be run together if 'validate_bd_design -force' is used:

    validate_bd_design -force
generate_target all [get_files design_1.bd]
AR# 67850
Date 06/18/2018
Status Active
Type Known Issues
  • Vivado Design Suite - 2016.2
  • Vivado Design Suite - 2016.3
  • Vivado Design Suite - 2016.4
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  • Vivado Design Suite - 2017.1
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