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AR# 67933

UltraScale/UltraScale+ Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part


Version Found: DDR4 v2.1, DDR3 v1.3, RLDRAM3 v1.3, QDRII+ v1.3, QDRIV v1.2

Version Resolved: See (Xilinx Answer 58435)

When a project containing Memory IP configured with a custom part is archived, moved, and then un-archived, the example design generated for the IP from the un-archived project fails during synthesis with the below errors:

ERROR: [Synth 8-439] module 'my_mig_phy' not found [/proj/dsv_xhd/pparata/ddr3_arch/ex_proj/my_mig_ex/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig_ddr3_mem_intfc.sv:595]
ERROR: [Synth 8-285] failed synthesizing module 'my_mig_ddr3_mem_intfc' [/proj/dsv_xhd/pparata/ddr3_arch/ex_proj/my_mig_ex/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig_ddr3_mem_intfc.sv:70]
ERROR: [Synth 8-285] failed synthesizing module 'my_mig_ddr3' [/proj/dsv_xhd/pparata/ddr3_arch/ex_proj/my_mig_ex/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig_ddr3.sv:153]
ERROR: [Synth 8-285] failed synthesizing module 'my_mig' [/proj/dsv_xhd/pparata/ddr3_arch/ex_proj/my_mig_ex/my_mig_ex.srcs/sources_1/ip/my_mig/rtl/ip_top/my_mig.sv:73]


There are two available work-arounds for the issue:

  • Close and reopen the example project
  • Regenerate the Memory IP in the example project

Revision History:

09/26/2016 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 67933
Date 01/12/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite - 2016.3
  • MIG UltraScale
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