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AR# 6802

Coregen 2.1: How do I obtain a description for each Coregen core created?


General Description: Where can configuration information about a

core be obtained?


For each core generated, Coregen generates an XCO file describing

the configuration of the core. The XCO file can be found in the

directory where the core was generated.

Here is an example of a Dual Port Fifo core:

# Xilinx CORE Generator 2.1i

# Username = John

# COREGenPath = e:\fndtn\coregen

# FoundationPath = e:\fndtn

# ProjectPath = E:\fndtn\Active\projects\MYCOREG

# ExpandedProjectPath = E:\fndtn\Active\projects\MYCOREG

SET BusFormat = BusFormatAngleBracket

SET SimulationOutputProducts = VHDL Verilog

SET ViewlogicLibraryAlias = ""

SET XilinxFamily = SPARTAN

SET DesignFlow = Schematic

SET FlowVendor = Foundation

SELECT Synchronous_FIFO SPARTAN Xilinx 1.0

CSET component_name = dualfifo

CSET data_width = 16

CSET dual_port = TRUE

CSET fifo_depth = 32


The CSET lines describe the component name, data width, fifo depth

and the type, single or dual port.
AR# 6802
Date Created 08/31/2007
Last Updated 03/22/2011
Status Archive
Type General Article