During simulation of a PCI or PCI-X LogiCORE, the parity lines appear unknowns or undefineds ("x"). Does this mean that the signal is not being properly driven during bus parking or some other time?
These "x"s are appearing as the result of a high-Z being pushed into a register. The HDL used to define parity generation does not include pull-ups or pull-downs; therefore, signals may go to high-z during simulation when in actual hardware implementation, they would instead be driven to a real value. These unknowns can be ignored and parity can be assumed to be driven as the spec requires, and to be driven properly.