UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 68369

2016.4 Vivado IP Release Notes - All IP Change Log Information Article

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2016.4 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2016 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

DISCLAIMER

This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

CRITICAL APPLICATIONS

Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.

10G Ethernet MAC (15.1)

*Version 15.1 (Rev. 2)

*No changes

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

*Version 6.0 (Rev. 7)

*Revision change in one or more subcores

10G Ethernet Subsystem (3.1)

*Version 3.1 (Rev. 3)

*General: Refer to ten_gig_eth_mac_v15_1 and ten_gig_eth_pcs_pma_v6_0 core change logs for changes in the sub cores of this core.

*General: No functional changes

*Revision change in one or more subcores

10G/25G Ethernet Subsystem (2.0)

*Version 2.0 (Rev. 1)

*Feature Enhancement: QPLL reset signals connected as per GTWIZ user guide recommendation

*Feature Enhancement: CR fixes

*Revision change in one or more subcores

1G/2.5G Ethernet PCS/PMA or SGMII (16.0)

*Version 16.0 (Rev. 1)

*Bug fix for clock correction in RX elastic buffer for Asynchronous LVDS modes.

*Updates in constraints for SGMII mode when interfaced with GEM.

*For 7 Series LVDS transceiver dependency of Transmitter reset on PHY loss of sync removed.

*Revision change in one or more subcores

32-bit Initiator/Target for PCI (7-Series) (5.0)

*Version 5.0 (Rev. 8)

*No changes

3GPP LTE Channel Estimator (2.0)

*Version 2.0 (Rev. 12)

*No changes

3GPP LTE MIMO Decoder (3.0)

*Version 3.0 (Rev. 12)

*No changes

3GPP LTE MIMO Encoder (4.0)

*Version 4.0 (Rev. 11)

*No changes

3GPP Mixed Mode Turbo Decoder (2.0)

*Version 2.0 (Rev. 12)

*No changes

3GPP Turbo Encoder (5.0)

*Version 5.0 (Rev. 11)

*No changes

3GPPLTE Turbo Encoder (4.0)

*Version 4.0 (Rev. 11)

*No changes

40G/50G Ethernet Subsystem (2.0)

*Version 2.0 (Rev. 1)

*Port Change: rxrecclkout ports added

*Port Change: stat_rx_fifo_error ports added

*Feature Enhancement: CR

*Revision change in one or more subcores

64-bit Initiator/Target for PCI (7 Series) (5.0)

*Version 5.0 (Rev. 8)

*No changes

7 Series FPGAs Transceivers Wizard (3.6)

*Version 3.6 (Rev. 5)

*General: Added support for XC7A12TCPG236 and XC7A25TCPG236 devices

7 Series Integrated Block for PCI Express (3.3)

*Version 3.3 (Rev. 3)

*General: Added support for xc7a12tl and xc7a25tl devices

*Revision change in one or more subcores

AHB-Lite to AXI Bridge (3.0)

*Version 3.0 (Rev. 9)

*Revision change in one or more subcores

AXI 1G/2.5G Ethernet Subsystem (7.0)

*Version 7.0 (Rev. 7)

*General: No functional changes.

*General: Refer to tri_mode_ethernet_mac v9.0 and gig_ethernet_pcs_pma v16_0 core change logs for changes in the sub cores of this core.

*Revision change in one or more subcores

AXI AHB-Lite Bridge (3.0)

*Version 3.0 (Rev. 9)

*Revision change in one or more subcores

AXI AMM Bridge (1.0)

*Version 1.0 (Rev. 1)

*Revision change in one or more subcores

AXI APB Bridge (3.0)

*Version 3.0 (Rev. 9)

*Revision change in one or more subcores

AXI BFM Cores (5.0)

*Version 5.0 (Rev. 7)

*No changes

AXI BRAM Controller (4.0)

*Version 4.0 (Rev. 10)

*Revision change in one or more subcores

AXI Bridge for PCI Express Gen3 Subsystem (3.0)

*Version 3.0 (Rev. 1)

*Bug Fix: Changed cfg_power_state_change_ack tie-off to 1 to allow non-D0 PCIe power state change initiated from Root

*Feature Enhancement: Added Narrow Burst support on S_AXI interface

*Revision change in one or more subcores

AXI CAN (5.0)

*Version 5.0 (Rev. 14)

*Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

*Version 4.1 (Rev. 11)

*Feature Enhancement: Enabled optional Store and Forward feature

*Revision change in one or more subcores

AXI Chip2Chip Bridge (4.2)

*Version 4.2 (Rev. 11)

*Revision change in one or more subcores

AXI Clock Converter (2.1)

*Version 2.1 (Rev. 10)

*Revision change in one or more subcores

AXI Crossbar (2.1)

*Version 2.1 (Rev. 12)

*Revision change in one or more subcores

AXI Data FIFO (2.1)

*Version 2.1 (Rev. 10)

*Revision change in one or more subcores

AXI Data Width Converter (2.1)

*Version 2.1 (Rev. 11)

*Revision change in one or more subcores

AXI DataMover (5.1)

*Version 5.1 (Rev. 13)

*General: XDC file updated to set correct value for set_bus_skew constraint

*Revision change in one or more subcores

AXI Direct Memory Access (7.1)

*Version 7.1 (Rev. 12)

*Revision change in one or more subcores

AXI EMC (3.0)

*Version 3.0 (Rev. 11)

*Revision change in one or more subcores

AXI EPC (2.0)

*Version 2.0 (Rev. 14)

*Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

*Version 2.0 (Rev. 14)

*Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

*Version 2.0 (Rev. 2)

*No changes

AXI Ethernet Lite (3.0)

*Version 3.0 (Rev. 9)

*Internal proc update. No functional changes.

*Revision change in one or more subcores

AXI GPIO (2.0)

*Version 2.0 (Rev. 13)

*Revision change in one or more subcores

AXI HWICAP (3.0)

*Version 3.0 (Rev. 15)

*Revision change in one or more subcores

AXI IIC (2.0)

*Version 2.0 (Rev. 14)

*Revision change in one or more subcores

AXI Interconnect (2.1)

*Version 2.1 (Rev. 12)

*Revision change in one or more subcores

AXI Interrupt Controller (4.1)

*Version 4.1 (Rev. 9)

*General: Corrected tooltip and warning messages

AXI Lite IPIF (3.0)

*Version 3.0 (Rev. 4)

*No changes

AXI MMU (2.1)

*Version 2.1 (Rev. 9)

*Revision change in one or more subcores

AXI Master Burst (2.0)

*Version 2.0 (Rev. 7)

*No changes

AXI Memory Mapped To PCI Express (2.8)

*Version 2.8 (Rev. 3)

*Bug Fix: Fixed AXI Slave interface stalling in 128-bit AXI configuration due to Completion Timeout/URs

*Bug Fix: Fixed INTx missing issue when both MSI and INTx arrive at the same time

*Other: Removed write restriction to Memory Limit/Base registers (Offset 0x20) in Type 1 PCI Configuration Space

*Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

*Version 1.1 (Rev. 10)

*Revision change in one or more subcores

AXI Performance Monitor (5.0)

*Version 5.0 (Rev. 13)

*Revision change in one or more subcores

AXI Protocol Checker (1.1)

*Version 1.1 (Rev. 12)

*Revision change in one or more subcores

AXI Protocol Converter (2.1)

*Version 2.1 (Rev. 11)

*Revision change in one or more subcores

AXI Quad SPI (3.2)

*Version 3.2 (Rev. 10)

*Example design update for XIP mode. No functional changes

*Revision change in one or more subcores

AXI Register Slice (2.1)

*Version 2.1 (Rev. 11)

*Revision change in one or more subcores

AXI SmartConnect (1.0)

*Version 1.0 (Rev. 3)

*Resolved various bugs.

*Revision change in one or more subcores

AXI TFT Controller (2.0)

*Version 2.0 (Rev. 15)

*Revision change in one or more subcores

AXI Timebase Watchdog Timer (3.0)

*Version 3.0 (Rev. 3)

*Revision change in one or more subcores

AXI Timer (2.0)

*Version 2.0 (Rev. 13)

*Revision change in one or more subcores

AXI Traffic Generator (2.0)

*Version 2.0 (Rev. 12)

*Revision change in one or more subcores

AXI UART16550 (2.0)

*Version 2.0 (Rev. 13)

*Revision change in one or more subcores

AXI USB2 Device (5.0)

*Version 5.0 (Rev. 12)

*Revision change in one or more subcores

AXI UART Lite (2.0)

*Version 2.0 (Rev. 15)

*Revision change in one or more subcores

AXI Verification IP (1.0)

*Version 1.0

*Initial Release

AXI Video Direct Memory Access (6.2)

*Version 6.2 (Rev. 10)

*Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

*Version 2.0 (Rev. 13)

*Revision change in one or more subcores

AXI-Stream FIFO (4.1)

*Version 4.1 (Rev. 8)

*Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

*Version 2.1 (Rev. 10)

*Revision change in one or more subcores

AXI4-Stream Broadcaster (1.1)

*Version 1.1 (Rev. 11)

*Revision change in one or more subcores

AXI4-Stream Clock Converter (1.1)

*Version 1.1 (Rev. 12)

*Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

*Version 1.1 (Rev. 10)

*Revision change in one or more subcores

AXI4-Stream Data FIFO (1.1)

*Version 1.1 (Rev. 12)

*Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

*Version 1.1 (Rev. 10)

*Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

*Version 2.1 (Rev. 12)

*Revision change in one or more subcores

AXI4-Stream Protocol Checker (1.1)

*Version 1.1 (Rev. 11)

*Revision change in one or more subcores

AXI4-Stream Register Slice (1.1)

*Version 1.1 (Rev. 11)

*Revision change in one or more subcores

AXI4-Stream Subset Converter (1.1)

*Version 1.1 (Rev. 11)

*Revision change in one or more subcores

AXI4-Stream Switch (1.1)

*Version 1.1 (Rev. 11)

*Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

*Version 4.0 (Rev. 5)

*Revision change in one or more subcores

Accumulator (12.0)

*Version 12.0 (Rev. 10)

*No changes

Adder/Subtracter (12.0)

*Version 12.0 (Rev. 10)

*No changes

Aurora 64B66B (11.1)

*Version 11.1 (Rev. 3)

*Revision change in one or more subcores

Aurora 8B10B (11.0)

*Version 11.0 (Rev. 7)

*General: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti devices

*Revision change in one or more subcores

Binary Counter (12.0)

*Version 12.0 (Rev. 10)

*No changes

Block Memory Generator (8.3)

*Version 8.3 (Rev. 5)

*General: Fixes for behavioral Model issues when built-in ECC is enabled (to be consistent with RTL)

CANFD (1.0)

*Version 1.0 (Rev. 4)

*Revision change in one or more subcores

CIC Compiler (4.0)

*Version 4.0 (Rev. 11)

*No changes

CORDIC (6.0)

*Version 6.0 (Rev. 11)

*No changes

CPRI (8.7)

*Version 8.7 (Rev. 1)

*Bug Fix: Fixed issue with FEC capable slave cores reporting stat_speed output incorrectly for FEC line rates.

*Bug Fix: Fixed issue with FEC capable slave cores incorrectly applying capability register changes for FEC line rates.

*Bug Fix: Fixed incorrect timing constraints on 7-series cores with maximum line rates of 8.11008Gbps and 0.6144Gbps.

*Revision change in one or more subcores

Chroma Resampler (4.0)

*Version 4.0 (Rev. 11)

*Revision change in one or more subcores

Clocking Wizard (5.3)

*Version 5.3 (Rev. 3)

*Bug Fix: Internal GUI issues are fixed.

Color Correction Matrix (6.0)

*Version 6.0 (Rev. 12)

*Revision change in one or more subcores

Color Filter Array Interpolation (7.0)

*Version 7.0 (Rev. 11)

*Revision change in one or more subcores

Complex Multiplier (6.0)

*Version 6.0 (Rev. 12)

*No changes

Convolution Encoder (9.0)

*Version 9.0 (Rev. 11)

*No changes

DDR3 SDRAM (MIG) (1.3)

*Version 1.3 (Rev. 1)

*Bug Fix: PFD range checks in GUI for Manual M and D Reference Input clock selection.

*Bug Fix: Old PHY IPs Update to fix the Phy core generation & Stitching Optimization error in Locked IP Upgrade flow.

*Bug Fix: (Xilinx Answer 67957) UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IP

*Bug Fix: (Xilinx Answer 67891) DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode

*Revision change in one or more subcores

DDR4 SDRAM (MIG) (2.1)

*Version 2.1 (Rev. 1)

*Bug Fix: PFD range checks in GUI for Manual M and D Reference Input clock selection.

*Bug Fix: Old PHY IPs Update to fix the Phy core generation & Stitching Optimization error in Locked IP Upgrade flow.

*Bug Fix: 3DS parts performance simulation Updates

*Bug Fix: DDR4 Self Refresh/Save Restore update for Multi rank design

*Bug Fix: (Xilinx Answer 67957) UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IP

*Bug Fix: (Xilinx Answer 67933) UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.

*Bug Fix: (Xilinx Answer 67891) DDR4/DDR3 IP - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode

*Revision change in one or more subcores

DDS Compiler (6.0)

*Version 6.0 (Rev. 13)

*No changes

DMA/Bridge Subsystem for PCI Express (PCIe) (3.0)

*Version 3.0 (Rev. 1)

*Bug Fix: Fixed simulation issue with Vivado simulator

*Feature Enhancement: Added AXI Bridge functionality for UltraScale Plus family devices

*Feature Enhancement: Enabled x16g3 support for -2L speedgrades for xcvu9p - flga2104,flgb2104,flgc2104 and fsgd2104

*Revision change in one or more subcores

DSP48 Macro (3.0)

*Version 3.0 (Rev. 13)

*No changes

DUC/DDC Compiler (3.0)

*Version 3.0 (Rev. 11)

*No changes

Debug Bridge (1.1)

*Version 1.1 (Rev. 1)

*No change

*Revision change in one or more subcores

Decapsulator (1.0)

*Version 1.0 (Rev. 3)

*Feature Enhancement: Common Design packet_reformatter enhancement

*Revision change in one or more subcores

Discrete Fourier Transform (4.0)

*Version 4.0 (Rev. 12)

*No changes

DisplayPort (7.0)

*Version 7.0 (Rev. 3)

*General: Addition of new device package support

*Revision change in one or more subcores

DisplayPort RX Subsystem (2.0)

*Version 2.0 (Rev. 3)

*General: Addition of new device package support

*Revision change in one or more subcores

DisplayPort TX Subsystem (2.0)

*Version 2.0 (Rev. 3)

*General: Cleaned up device support for GTYE4

*General: Addition of new device package support

*Revision change in one or more subcores

Distributed Memory Generator (8.0)

*Version 8.0 (Rev. 11)

*No changes

Divider Generator (5.1)

*Version 5.1 (Rev. 11)

*No changes

Double Data Rate Sampling (1.0)

*Version 1.0

*No changes

ECC (2.0)

*Version 2.0 (Rev. 12)

*No changes

Ethernet PHY MII to Reduced MII (2.0)

*Version 2.0 (Rev. 13)

*Revision change in one or more subcores

FIFO Generator (13.1)

*Version 13.1 (Rev. 3)

*Port Change: None

*Bug Fix: Fixed issue which was causing the m_axis_tvalid to go high after the reset is released and no valid data written to the FIFO

*Feature Enhancement: None

*Revision change in one or more subcores

FIR Compiler (7.2)

*Version 7.2 (Rev. 7)

*No changes

Fast Fourier Transform (9.0)

*Version 9.0 (Rev. 11)

*No changes

Fibre Channel 32GFC RS-FEC (1.0)

*Version 1.0 (Rev. 1)

*General: Added support for UltraScale+ -2LV speed grade

Fixed Interval Timer (2.0)

*Version 2.0 (Rev. 8)

*No changes

FlexO 100G RS-FEC (1.0)

*Version 1.0 (Rev. 1)

*General: Added support for UltraScale+ -2LV speed grade.

*General: Internal enhancements to improve synthesis. No change in behavior.

*Revision change in one or more subcores

Floating-point (7.1)

*Version 7.1 (Rev. 3)

*No changes

Framer (1.0)

*Version 1.0 (Rev. 3)

*Feature Enhancement: Common Design packet_reformatter enhancement

G.709 FEC Encoder/Decoder (2.2)

*Version 2.2 (Rev. 6)

*General: Removal of support for UltraScale Plus -1 speed grade as speed files have matured.

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

*Version 1.0 (Rev. 13)

*No changes

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

*Version 2.0 (Rev. 13)

*No changes

Gamma Correction (7.0)

*Version 7.0 (Rev. 12)

*Revision change in one or more subcores

GMII to RGMII (4.0)

*Version 4.0 (Rev. 3)

*No changes

HDCP (1.0)

*Version 1.0 (Rev. 1)

*No changes

HDCP 2.2 Cipher (1.0)

*Version 1.0

*No changes

HDCP 2.2 Montgomery Modular Multiplier (1.0)

*Version 1.0

*No changes

HDCP 2.2 Random Number Generator (1.0)

*Version 1.0 (Rev. 1)

*No changes

HDCP 2.2 Receiver (1.0)

*Version 1.0 (Rev. 2)

*No changes

HDCP 2.2 Transmitter (1.0)

*Version 1.0 (Rev. 2)

*No changes

HDMI 1.4/2.0 Receiver (1.1)

*Version 1.1

*No changes

HDMI 1.4/2.0 Receiver Subsystem (2.0)

*Version 2.0 (Rev. 3)

*Feature Enhancement: Added Vivado Example Design support for ZC706 Board.

HDMI 1.4/2.0 Transmitter (1.1)

*Version 1.1

*No changes

HDMI 1.4/2.0 Transmitter Subsystem (2.0)

*Version 2.0 (Rev. 3)

*Feature Enhancement: Added Vivado Example Design support for ZC706 Board.

High Speed SelectIO Wizard (3.1)

*Version 3.1 (Rev. 1)

*Bug Fix: Modified Rx Delay Mode selection. It is enabled in GUI only for Async Mode

IBERT 7 Series GTH (3.0)

*Version 3.0 (Rev. 15)

*Added synchronizer for reset signal in accumulator logic.

*Revision change in one or more subcores

IBERT 7 Series GTP (3.0)

*Version 3.0 (Rev. 14)

*Added support for Whistler and low power devices.

*Revision change in one or more subcores

IBERT 7 Series GTX (3.0)

*Version 3.0 (Rev. 15)

*Added synchronizer for reset signal in accumulator logic

*Revision change in one or more subcores

IBERT 7 Series GTZ (3.1)

*Version 3.1 (Rev. 12)

*Added synchronizer for reset signal in accumulator logic

IBERT UltraScale GTH (1.3)

*Version 1.3 (Rev. 5)

*Updated synthesis wrapper to divide core generation info into multiple lines.

*Revision change in one or more subcores

IBERT UltraScale GTY (1.2)

*Version 1.2 (Rev. 5)

*Updated synthesis wrapper to divide core generation info into multiple lines.

*Revision change in one or more subcores

IEEE 802.3 25G RS-FEC (1.0)

*Version 1.0 (Rev. 3)

*General: Internal enhancements to improve timing. No change in behavior.

*Revision change in one or more subcores

IEEE 802.3 50G RS-FEC (1.0)

*Version 1.0 (Rev. 3)

*General: Added support for UltraScale+ -2LV speed grade

*Revision change in one or more subcores

IEEE 802.3bj RS-FEC (1.0)

*Version 1.0 (Rev. 7)

*General: Added support for UltraScale+ -2LV speed grade

*General: Internal enhancements to improve timing and reduce size. No change in behavior.

*Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.2)

*Version 6.2 (Rev. 1)

*Updated ILA and Debug Hub IPs to handle CDC warnings

*Revision change in one or more subcores

IOModule (3.0)

*Version 3.0 (Rev. 6)

*No changes

Image Enhancement (8.0)

*Version 8.0 (Rev. 12)

*Revision change in one or more subcores

In System IBERT (1.0)

*Version 1.0 (Rev. 1)

*Updated GT type in IP GUI summary page.

*Revision change in one or more subcores

Interlaken up to 150G (2.0)

*Version 2.0 (Rev. 1)

*Port Change: gtwiz_reset_tx_datapath and gtwiz_reset_rx_datapath ports made visible for all configurations

*Feature Enhancement: CR fixes

*Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

*Version 8.0 (Rev. 10)

*No changes

JESD204 (7.1)

*Version 7.1 (Rev. 1)

*Feature Enhancement: Optimized core logic for synthesis speed improvement

*Revision change in one or more subcores

JESD204 PHY (3.2)

*Version 3.2 (Rev. 1)

*Feature Enhancement: Modified GUI not to set max line rate parameter to device's max line rate

*Revision change in one or more subcores

JTAG to AXI Master (1.2)

*Version 1.2 (Rev. 1)

*Revision change in one or more subcores

LMB BRAM Controller (4.0)

*Version 4.0 (Rev. 10)

*No changes

LTE DL Channel Encoder (3.0)

*Version 3.0 (Rev. 11)

*No changes

LTE Fast Fourier Transform (2.0)

*Version 2.0 (Rev. 12)

*No changes

LTE PUCCH Receiver (2.0)

*Version 2.0 (Rev. 11)

*No changes

LTE RACH Detector (2.0)

*Version 2.0 (Rev. 11)

*No changes

LTE UL Channel Decoder (4.0)

*Version 4.0 (Rev. 11)

*No changes

Local Memory Bus (LMB) 1.0 (3.0)

*Version 3.0 (Rev. 9)

*No changes

MIPI CSI-2 Rx Controller (1.0)

*Version 1.0 (Rev. 5)

*Revision change in one or more subcores

MIPI CSI-2 Rx Subsystem (2.1)

*Version 2.1 (Rev. 1)

*Port Change: Added new ports based on Calibration mode parameter

*Port Change: Removed mmcm_lock_out port due to MMCM removal from MIPI DPHY

*Bug Fix: Fixed issue with Calibration mode parameters getting updated for MIPI D-PHY

*Bug Fix: Improved lane to lane skew tolerance from 2 rxbyteclkhs to 6 rxbyteclkhs

*Revision change in one or more subcores

MIPI CSI-2 Tx Controller (1.0)

*Version 1.0 (Rev. 1)

*Revision change in one or more subcores

MIPI CSI-2 Tx Subsystem (1.0)

*Version 1.0 (Rev. 1)

*Bug Fix: Fixed the Word-count 0,1,2 issue in Lane Distribution Block for 3,4 lanes

*Bug Fix: Fixed the resetting of internal states in RGB888 Data Type interleaving case

*Revision change in one or more subcores

MIPI D-PHY (3.0)

*Version 3.0 (Rev. 1)

*Port Change: Added clk_300m port for 7-Series Auto Calibration mode (See Product Guide PG202 "Port Descriptions" section for list of added ports.)

*Port Change: Updated 7-Series Calibration mode ports (See Product Guide PG202 "Port Descriptions" section for list of added ports.)

*Bug Fix: BUFG insertion on FIFO_WRCLK_OUT for HOLD time violations in D-PHY RX IP

*Bug Fix: Fixed Data Lane HS-RX TD-TERM-EN value for D-PHY RX Compliance Test 2.4.1

*Bug Fix: Fixed Clock Lane HS-RX TCLK-TERM-EN value for D-PHY RX Compliance Test 2.4.6

*Bug Fix: Updated the Auto Calibration mode with per-bit deskew for 7-Series D-PHY RX IP

*Bug Fix: Removed MMCM for UltraScale+ D-PHY RX IP configuration and using constant 1500 MHz CLKOUTPHY for all line rates

*Revision change in one or more subcores

MIPI DSI Tx Controller (1.0)

*Version 1.0 (Rev. 3)

*Revision change in one or more subcores

MIPI DSI Tx Subsystem (1.1)

*Version 1.1 (Rev. 1)

*Bug Fix: Line time register read value corrected when HBP or HFP is 0

*Revision change in one or more subcores

Mailbox (2.1)

*Version 2.1 (Rev. 7)

*No changes

Memory Helper Core (1.3)

*Version 1.3

*No changes

Memory Interface Generator (MIG 7 Series) (4.0)

*Version 4.0 (Rev. 2)

*General: Vivado 2016.4 software support.

MicroBlaze (10.0)

*Version 10.0 (Rev. 1)

*General: Modify HDL to avoid tool warnings, no functional changes

MicroBlaze Debug Module (MDM) (3.2)

*Version 3.2 (Rev. 8)

*General: Modify HDL to avoid tool warnings, no functional changes

MicroBlaze MCS (3.0)

*Version 3.0 (Rev. 3)

*Revision change in one or more subcores

Multiplier (12.0)

*Version 12.0 (Rev. 12)

*No changes

Multiply Adder (3.0)

*Version 3.0 (Rev. 10)

*No changes

Mutex (2.1)

*Version 2.1 (Rev. 8)

*No changes

PCIe PHY IP (1.0)

*Version 1.0 (Rev. 3)

*Feature Enhancement: Enabled CPLL CAL block in GT_wizard and related logic

*Revision change in one or more subcores

Partial Reconfiguration Controller (1.1)

*Version 1.1 (Rev. 1)

*Revision change in one or more subcores

Partial Reconfiguration Decoupler (1.0)

*Version 1.0 (Rev. 3)

*No changes

Peak Cancellation Crest Factor Reduction (6.1)

*Version 6.1

*No changes

Processor System Reset (5.0)

*Version 5.0 (Rev. 10)

*No changes

QDRII+ SRAM (MIG) (1.3)

*Version 1.3 (Rev. 1)

*Bug Fix: PFD range checks in GUI for Manual M and D Reference Input clock selection.

*Bug Fix: Old PHY IPs Update to fix the Phy core generation & Stitching Optimization error in Locked IP Upgrade flow.

*Revision change in one or more subcores

QDRIV SRAM (MIG) (1.2)

*Version 1.2 (Rev. 1)

*Bug Fix: PFD range checks in GUI for Manual M and D Reference Input clock selection.

*Bug Fix: Old PHY IPs Update to fix the Phy core generation & Stitching Optimization error in Locked IP Upgrade flow.

*Revision change in one or more subcores

QDRIV SRAM PHY IP (1.2)

*Version 1.2

*No changes

QSGMII (3.3)

*Version 3.3 (Rev. 7)

*Revision change in one or more subcores

RAM-based Shift Register (12.0)

*Version 12.0 (Rev. 10)

*No changes

RFC3190 De-Packetizer (1.0)

*Version 1.0

*No changes

RFC3190 Packetizer (1.0)

*Version 1.0

*No changes

RFC4175 De-packetizer (1.0)

*Version 1.0

*No changes

RFC4175 Packetizer (1.0)

*Version 1.0

*No changes

RGB to YCrCb Color-Space Converter (7.1)

*Version 7.1 (Rev. 10)

*Revision change in one or more subcores

RLDRAM3 (MIG) (1.3)

*Version 1.3 (Rev. 1)

*Bug Fix: PFD range checks in GUI for Manual M and D Reference Input clock selection.

*Bug Fix: Old PHY IPs Update to fix the Phy core generation & Stitching Optimization error in Locked IP Upgrade flow.

*Revision change in one or more subcores

RXAUI (4.3)

*Version 4.3 (Rev. 7)

*Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

*Version 9.0 (Rev. 12)

*No changes

Reed-Solomon Encoder (9.0)

*Version 9.0 (Rev. 11)

*No changes

S/PDIF (2.0)

*Version 2.0 (Rev. 14)

*Revision change in one or more subcores

SC EXIT (1.0)

*Version 1.0 (Rev. 3)

*Revision change in one or more subcores

SC MMU (1.0)

*Version 1.0 (Rev. 3)

*Revision change in one or more subcores

SC SI_CONVERTER (1.0)

*Version 1.0 (Rev. 3)

*Feature Enhancement: Optimized timing paths for narrow read burst packing and for read/write packet mode (WATERMARK).

*Revision change in one or more subcores

SC SPLITTER (1.0)

*Version 1.0 (Rev. 2)

*Revision change in one or more subcores

SC TRANSACTION_REGULATOR (1.0)

*Version 1.0 (Rev. 3)

*Feature Enhancement: Optimized timing paths for multi-threaded read/write transactions.

*Revision change in one or more subcores

SMPTE 2022-1/2 Video over IP Receiver (2.0)

*Version 2.0 (Rev. 8)

*Revision change in one or more subcores

SMPTE 2022-1/2 Video over IP Transmitter (2.0)

*Version 2.0 (Rev. 8)

*Revision change in one or more subcores

SMPTE SD/HD/3G-SDI (3.0)

*Version 3.0 (Rev. 8)

*No changes

SMPTE ST 2059 (1.0)

*Version 1.0 (Rev. 1)

*No changes

SMPTE UHD-SDI (1.0)

*Version 1.0 (Rev. 3)

*No changes

SMPTE2022-5/6 Video over IP Receiver (5.0)

*Version 5.0 (Rev. 7)

*Revision change in one or more subcores

SMPTE2022-5/6 Video over IP Transmitter (4.0)

*Version 4.0 (Rev. 9)

*Revision change in one or more subcores

SPI-4.2 (13.0)

*Version 13.0 (Rev. 9)

*No changes

ST2022-56 De-Packetizer (1.0)

*Version 1.0 (Rev. 3)

*Feature Enhancement: Common Design packet_reformatter enhancement

ST2022-56 Packetizer (1.0)

*Version 1.0 (Rev. 3)

*Bug Fix: Adds NULL on the remainder packet after the marker packet

*Feature Enhancement: Common Design packet_reformatter enhancement

SelectIO Interface Wizard (5.1)

*Version 5.1 (Rev. 8)

*No changes

Serial RapidIO Gen2 (4.0)

*Version 4.0 (Rev. 6)

*Feature Enhancement: Added support for CPG236 package for 7A25T and 7A12T devices

*Revision change in one or more subcores

SmartConnect AXI2SC Bridge (1.0)

*Version 1.0 (Rev. 3)

*Revision change in one or more subcores

SmartConnect Node (1.0)

*Version 1.0 (Rev. 3)

*Formatting changes.

*Revision change in one or more subcores

SmartConnect SC2AXI Bridge (1.0)

*Version 1.0 (Rev. 3)

*Revision change in one or more subcores

SmartConnect Switchboard (1.0)

*Version 1.0 (Rev. 3)

*Revision change in one or more subcores

Soft Error Mitigation (4.1)

*Version 4.1 (Rev. 7)

*No changes

System Cache (4.0)

*Version 4.0 (Rev. 1)

*Bug Fix: Fixed issue that could cause WriteBack to be classified as WriteUnique. Version that has this issue: 4.0. Can only occur when C_COHERENCY is set to 2.

*Bug Fix: Snoop with conflict could sometimes fail to update cache line properties. Version that has this issue: 4.0. Can only occur when C_COHERENCY is set to 2.

*Feature Enhancement: Increase write buffer size

*Feature Enhancement: Added WriteBack snoop extraction

*Feature Enhancement: Added pipelining to improve timing for master coherent configuration

System ILA (1.0)

*Version 1.0 (Rev. 1)

*Revision change in one or more subcores

System Management Wizard (1.3)

*Version 1.3 (Rev. 3)

*General: Added web talk data, no effect on the customer designs.

Timer Sync 1588 (1.2)

*Version 1.2 (Rev. 4)

*No changes

Tri Mode Ethernet MAC (9.0)

*Version 9.0 (Rev. 6)

*No changes

UltraScale 100G Ethernet Subsystem (2.0)

*Version 2.0 (Rev. 1)

*Port Change: Changed the axi_gt_loopback signal to ctl_gt_loopback

*Other: Removed the clock root constraints from the core XDC as the rules are updated in the SW

*Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.2)

*Version 4.2 (Rev. 3)

*Bug Fix: Timing issue is fixed by adding register on user_reset and user_lnk_up signals.

*Bug Fix: Updated Tandem with Field Updates floorplans to improve placement and timing.

*Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.6)

*Version 1.6 (Rev. 5)

*General: Updated the line rate ranges for some speed grade devices to match the UltraScale+ FPGAs Data sheet

*General: Updated the CPLL calibration module for PCIe use modes for UltraScale+ devices

*Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.1)

*Version 3.1 (Rev. 2)

*No changes

UltraScale+ 100G Ethernet Subsystem (2.1)

*Version 2.1

*Port Change: Changed the axi_gt_loopback signal to ctl_gt_loopback

*Feature Enhancement: Added support for TX Interpacket Gap (IPG) value parameter configuration in GUI

*Revision change in one or more subcores

UltraScale+ PCI Express Integrated Block (1.1)

*Version 1.1 (Rev. 3)

*Port Change: No

*Bug Fix: Fixed PF-1 settings edit issue when MSI-X is enabled.

*Bug Fix: Fixed Root Port as DUT simulation issue when the configuration is Gen3x16 and RQ/RC, 4TLP straddle is enabled.

*Feature Enhancement: No

*Other: MSI-X TABLE/PBA OFFSET address shifted to right by 3-bits to match PCIe Hard Block requirement.

*Revision change in one or more subcores

VIO (Virtual Input/Output) (3.0)

*Version 3.0 (Rev. 14)

*Revision change in one or more subcores

Video AXI4S Remapper (1.0)

*Version 1.0 (Rev. 2)

*No changes

Video Color Space Conversion and Correction (1.0)

*Version 1.0 (Rev. 5)

*Revision change in one or more subcores

Video Deinterlacer (4.0)

*Version 4.0 (Rev. 11)

*No changes

Video In to AXI4-Stream (4.0)

*Version 4.0 (Rev. 5)

*Revision change in one or more subcores

Video Mixer (1.0)

*Version 1.0 (Rev. 3)

*Revision change in one or more subcores

Video On Screen Display (6.0)

*Version 6.0 (Rev. 13)

*Revision change in one or more subcores

Video PHY Controller (2.0)

*Version 2.0 (Rev. 4)

*General: Enable HDMI fast switching support in IP Integrator block design

Video Processing Subsystem (2.0)

*Version 2.0 (Rev. 3)

*Revision change in one or more subcores

Video Test Pattern Generator (7.0)

*Version 7.0 (Rev. 5)

*Revision change in one or more subcores

Video Timing Controller (6.1)

*Version 6.1 (Rev. 10)

*Bug Fix: Fixed problem with AXI4-Lite error response being generated for low resolution video formats.

*Feature Enhancement: Added support for 8K video formats.

Video over IP FEC Receiver (2.0)

*Version 2.0 (Rev. 3)

*General: Small update in buffer depth handler

*Revision change in one or more subcores

Video over IP FEC Transmitter (2.0)

*Version 2.0 (Rev. 3)

*Feature Enhancement: Common Design packet_reformatter enhancement

*Revision change in one or more subcores

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.2)

*Version 4.2 (Rev. 3)

*Revision change in one or more subcores

Viterbi Decoder (9.1)

*Version 9.1 (Rev. 7)

*No changes

XADC Wizard (3.3)

*Version 3.3 (Rev. 2)

*General: VREFP register value updated.

XAUI (12.2)

*Version 12.2 (Rev. 7)

*Revision change in one or more subcores

XHMC (1.0)

*Version 1.0 (Rev. 1)

*Bug Fix: Remove pmareset_done from MMCM reset to enhance reset stability for full-width GTY link

*Bug Fix: Disable Half-width configuration for VCU110 link 0

*Bug Fix: Add JTAG-AXI debugger module to access HMC device registers through IIC

*Bug Fix: Change GT Insertion loss setting for VCU110 board from 8 to 4

*Other: Fixed bitstream warning regarding the clock_delay_group

*Revision change in one or more subcores

YCrCb to RGB Color-Space Converter (7.1)

*Version 7.1 (Rev. 10)

*Revision change in one or more subcores

ZYNQ7 Processing System (5.5)

*Version 5.5 (Rev. 3)

*No changes

ZYNQ7 Processing System BFM (2.0)

*Version 2.0 (Rev. 5)

*No changes

Zynq UltraScale+ MPSoC (2.0)

*Version 2.0 (Rev. 1)

*Updated DDR4/LPDDR4/LPDDR3 timing parameters and drift settings for DDR configuration registers

axi_sg (4.1)

*Version 4.1 (Rev. 5)

*Revision change in one or more subcores

interrupt_controller (3.1)

*Version 3.1 (Rev. 4)

*No changes

lib_bmg (1.0)

*Version 1.0 (Rev. 7)

*Revision change in one or more subcores

lib_cdc (1.0)

*Version 1.0 (Rev. 2)

*No changes

lib_fifo (1.0)

*Version 1.0 (Rev. 7)

*Revision change in one or more subcores

lib_pkg (1.0)

*Version 1.0 (Rev. 2)

*No changes

lib_srl_fifo (1.0)

*Version 1.0 (Rev. 2)

*No changes

AR# 68369
Date 12/19/2016
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2016.4
Page Bookmarked