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AR# 6840

Exemplar - Spectrum 1998.2 is not inferring Xilinx Virtex flip-flops with both synchronous set and reset


Keywords: FDRSE, sync, set, reset, Virtex, Leonardo, flip, flop, infer

Urgency: Stanrdard

General Description:
I am describing a synchronous set and reset, which is valid in the Virtex architecture. After the optimize step, I am seeing the set signal and the data signal being implemented in a LUT instead of utilizing the Virtex-specific features. This is resulting in an increased LUT count, and area usage. (I am using Leonardo Spectrum 1998.2e.)


The Beta version contains fixes for inferring Xilinx Virtex flip-flops with synchronous set or reset. Currently, the Exemplar software cannot infer a Virtex-specific synchronous set and reset.

Possible work-arounds are to:

1. Instantiate the component.
2. Use the set include_gates "FDRSE FRSE FDRSE_1 FDSE_1" from the variable editor within the GUI or in the script.

NOTE: If Method 2 is used, the data and set signal may be swapped during synthesis; because of this, Step 1 is the recommended work-around.
AR# 6840
Date Created 06/22/1999
Last Updated 09/17/2002
Status Archive
Type General Article