UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6861

V2.1i COREGEN USER GUIDE, MTI, VHDL flow: 'Error xxxmyadder8.vhd(20): near "myadder8_top" expecting COMPONENT' in VHDL testbench example

Description

Keywords: coregen, user, guide, vhdl, component

Urgency: standard

General Description:
The MTI ModelSIM/VHDL simulator issues the following error on the sample
VHDL testbench file copied from the User Guide:

# ERROR: /<path_to_testbench_myadder8.vhd>(20): near "myadder8_top": expecting: COMPONENT

Solution

There is a syntax error in the example testbench file, testbench.vhd.
The END statement for the COMPONENT corresponding to the top level
design block should read,

END component;

instead of:

END myadder8_top;

AR# 6861
Date Created 06/23/1999
Last Updated 08/01/2001
Status Archive
Type General Article