For all device families in Vivado versions prior to 2016.3, it was discovered that the package flight time data was not used in Timing Analysis for differential I/O standards. The timing engine did not utilize the package flight times during the analysis of the differential I/O delays.
The only place that this would appear would be in a pin-to-pin timing constraint, and the discrepancy of 50-300ps should be inconsequential to meeting timing, as the path is dominated by the clock delay and the correct placement of the register in the I/O block.
The types of applications that are sensitive to pin-to-pin timing are system synchronous chip to chip interfaces (a common clock source between both devices FPGA and other). These interfaces are typically slow (sub 200MHz) which is why a 50 to 300ps error is considered inconsequential.
Because design interfaces with critical I/O timing use dedicated I/O registers (including ISERDES or OSERDES blocks) resulting in fixed setup, hold, and clock-to-out timing, there is minimal risk that retiming will create a timing failure using Vivado 2016.3 or higher. Designs using only single ended I/O standards are not affected.
2012.x, 2013.x, 2014.x, 2015.x, 2016.1, 2016.2
Affected Device families:
7 Series, UltraScale, UltraScale+
This issue has been fixed in Vivado 2016.3 and newer versions.
To work around this issue, use the timing analysis in Vivado 2016.4 and re-implement the design to meet timing if required.
04/14/2017 - 1.0 Initial Release