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AR# 69038

QDRII+ UltraScale and UltraScale+ IP Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the QDRII+ UltraScale and UltraScale+ Cores and includes the following:

  • Supported Devices
  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

MIG IP Page:



General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

QDRII+ VersionVivado Tools Version
v1.4 (Rev. 1)2017.2
v1.3 (Rev. 1)2016.4
v1.2 (Rev. 1)2016.2
v5.0 Rev12014.2

* Starting with the release of Vivado 2015.3, the MIG wizard is no longer used. A separate wizard exists for all supported memory interface types. Therefore, the core versions reset to 1.0.

For a list of supported memory interfaces and features for UltraScale FPGAs, see the LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide (PG150) located at:


For a complete list of supported memory devices please refer to the attached spreadsheet called "memory_device_support_qdriiplus.xlsx".

For a list of supported frequencies for UltraScale FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the UltraScale Documentation Center.

For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

The MIG tool includes the appropriate frequency range for each specific memory interface configuration

Table 2 provides answer records for general guidance when using the MIG UltraScale core.

Table 2: General Guidance

Answer RecordTitle
(Xilinx Answer 59625)MIG UltraScale - Design Methodology Checklist
(Xilinx Answer 61304)MIG UltraScale - Clocking Guidelines and Requirements
(PG150) - DebuggingMIG UltraScale DDR4/DDR3 - Hardware Debug Guide
(Xilinx Answer 63462)MIG UltraScale - Sample CSV data file for creating Custom Parts
(Xilinx Answer 63831)MIG UltraScale - Migrating and Upgrading IP into 2015.1
(Xilinx Answer 61598)Design Advisory Master Answer Record for Kintex UltraScale FPGA
(Xilinx Answer 61930)Design Advisory Master Answer Record for Virtex UltraScale FPGA
(Xilinx Answer 62483)Design Advisory for MIG UltraScale (all memory types) - VRP pin and DCI Cascade requirements
(Xilinx Answer 68169)Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - New minimum production speed specification version (Speed File) required for all designs

Known and Resolved Issues

The following table provides known issues for the MIG UltraScale core, starting with v5.0, initially released in the Vivado 2014.1 tool.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


The following table provides known issues for MIG UltraScale QDRII+ SRAM.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69291)UltraScale+ Memory IP - The SFVA625 package does not support PL Memory Interfacesv1.4v1.4 (Rev. 1)
(Xilinx Answer 68028)UltraScale Memory IP - Pulse width violations occur for designs that violate the maximum BUFGCE timing spec with the Reference Input Clock Speed (ps)v1.3v1.4
(Xilinx Answer 67959)UltraScale QDRII+ IP - XSDB reports Memory Frequency incorrectlyv1.2 (Rev. 1)Not Resolved
(Xilinx Answer 67336)UltraScale QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) modev1.2 (Rev. 1)Not Resolved
(Xilinx Answer 59990)MIG UltraScale - IP Integrator MIG simulation does not have memory models availablev5.0Never Fix
(Xilinx Answer 67392)UltraScale and UltraScale+ Memory IP - pulse width violations can occurv1.2 (Rev. 1)v1.4
(Xilinx Answer 67967)UltraScale Memory IP - Error: [Unisim MMCME3_ADV-10] The calculated PFD frequency=799.360512 Mhz. This exceeds the permitted PFD frequency rangev1.3v1.3 (Rev. 1)
(Xilinx Answer 67957)UltraScale Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IPv1.3v1.3 (Rev. 1)
(Xilinx Answer 67933)UltraScale Memory IP - Error messages generated after archiving and moving a project containing Memory IP with a custom part.v1.3v1.3 (Rev. 1)
(Xilinx Answer 67684)UltraScale Memory IP - moving IP that uses custom memory parts (CSV) might cause problemsv1.2 (Rev. 1)v1.3
(Xilinx Answer 67335)UltraScale+ Memory IP - devices fail during opt_design with custom memory part if generation of the IP output products is skippedv1.2 (Rev. 1)v1.3
(Xilinx Answer 67225)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint not automatically generated by IPv1.2v1.2 (Rev. 1)
(Xilinx Answer 66951)Memory IP - WARNING: [DRC 23-20] Rule violation (PDCN-1569) LUT equation term checkv1.2v1.3
(Xilinx Answer 66360)UltraScale Memory IP - Core Container does not include *.csv file when a custom memory part is createdv1.0v1.3
(Xilinx Answer 67224)UltraScale Memory IP - CLOCK_DEDICATED_ROUTE BACKBONE constraint must be applied to the CLKIN1 pin of the MMCMv1.2v1.2 (Rev. 1)
(Xilinx Answer 66678)UltraScale Memory IP - Design fails during 'opt_design' when using Custom CSVv1.1v1.2
(Xilinx Answer 65431)UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraintv1.0v1.2
(Xilinx Answer 62543)MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periodsv6.0v1.2
(Xilinx Answer 65370)Memory IP - pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located inv1.0v1.1
(Xilinx Answer 65327)UltraScale Memory IP - CRITICAL WARNING: [Xicom 50-38] xicom: The current version of Vivado does not support this detected version of the MIG core. 2015.2 is the last version supporting itv1.0v1.1
(Xilinx Answer 64778)MIG UltraScale - When using the Auto Assign feature of Bank Planner, an error message is not issued when the memory ports do not fit into a half bankv7.0v1.1
(Xilinx Answer 64188)MIG UltraScale - sys_rst missing set_false_path constraintv7.0v1.1
(Xilinx Answer 64071)MIG UltraScale - custom memory parts fail simulationv7.0v1.0
(Xilinx Answer 64923)MIG UltraScale - [Xicom 50-24] error message occurs after programing devicev7.0v1.3
(Xilinx Answer 64783)MIG UltraScale QDRII+ - XSDB Debugger indicates MicroBlaze has failed but calibration completesv7.0v1.0
(Xilinx Answer 64488)MIG UltraScale QDRII+ - core generation fails due to invalid Memory Device Interface Speed settingv7.0v7.1
(Xilinx Answer 64069)MIG UltraScale - The Memory Byte/Bank Planner does not honor previously set PROHIBIT pinsv7.0v7.1
(Xilinx Answer 64006)MIG UltraScale QDRII+ - unexpected DRC for correct placement of memory clock pair (K/K#)v7.0v7.1
(Xilinx Answer 63689)MIG UltraScale QDRII+ - Read latency 2.0 (RL2) and Burst length 2 (BL2) designs fail simulation with Cypress memory modelv7.0v7.1
(Xilinx Answer 64427)MIG UltraScale - calibration and intermittent data errors due to improper calibration resultsv6.1v7.0
(Xilinx Answer 64431)MIG UltraScale - ]Xicom 50-38] xicom: Invalid memory type value detected from MIG core: 0.v6.1v7.0
(Xilinx Answer 62774)MIG UltraScale - timing failures may be seen with MIG generated example designv6.1v7.0
(Xilinx Answer 64070)MIG UltraScale - designs with multiple controllers may generate ERROR::34 messagev6.1v7.0
(Xilinx Answer 63261)MIG UltraScale DDR3/DDR4/QDRII+ - Multi-driver errors found during Lint checkv6.1v7.0
(Xilinx Answer 62649)MIG UltraScale - GUI allows core generation even if all address and control byte lanes have not been selectedv6.0v7.0
(Xilinx Answer 59989)MIG UltraScale - Critical warnings are generated when multiple MIG instances are included in a designv5.0v7.0
(Xilinx Answer 59991)MIG UltraScale - When running QuestaSim simulation within the Vivado GUI, the simulation is not successful.v5.0v7.0
(Xilinx Answer 62157)Design Advisory for MIG UltraScale QDRII+ - pinout DRC violations not caught in I/O Plannerv5.0 Rev1v6.0
(Xilinx Answer 61696)MIG UltraScale - the funcsim.v/.vhdl structural simulation model is not supportedv5.0 Rev1N/A
(Xilinx Answer 61555)MIG UltraScale QDRII+ - multi-driver issue in Cypress model causes data error in simulationv5.0 Rev1N/A
(Xilinx Answer 61076)MIG UltraScale - Multiple instances of MIG IP fail with "[Place 30-678] Failed to do clock region partitioning"v5.0 Rev1v6.1
(Xilinx Answer 60953)MIG UltraScale - Output Products must be generated before opening the IP Example Designv5.0 Rev1v6.0
(Xilinx Answer 60951)MIG UltraScale RLDRAM3 and QDRII+ - timing failure from XiPHY to riu_clkv5.0 Rev 1v6.0
(Xilinx Answer 60047)MIG UltraScale QDRII+ - incorrect parameter values for 36-bit designs using x16 components

Revision History:

04/18/2017Created Separate Answer Record for QDRII+
06/12/2017Updated for 2017.2; Added AR68028, AR69291


Associated Attachments

Name File Size File Type
memory_device_support_qdriiplus.xlsx 16 KB XLSX

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 69038
Date 06/20/2017
Status Active
Type Release Notes
  • Vivado Design Suite
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