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AR# 69055

2017.1 Vivado IP Release Notes - All IP Change Log Information Article

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2017.1 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2017 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

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10G Ethernet MAC (15.1)

* Version 15.1 (Rev. 2)

* No changes

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 8)

* Bug Fix: Connected unused input ports GTTXRESET and GTRXRESET to corresponding GT interface pins

* Revision change in one or more subcores

10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 4)

* Bug Fix: Rectified clock associations with interfaces for shared logic in core

* Other: Refer to ten_gig_eth_mac_v15_1 and ten_gig_eth_pcs_pma_v6_0 core change logs for changes in the sub cores of this core

* Other: No functional changes

* Revision change in one or more subcores

10G/25G Ethernet Subsystem (2.1)

* Version 2.1

* Feature Enhancement: QPLL reset signals connected as per GTWIZ User Guide recommendation

* Feature Enhancement: Added BUFG_GT to drive gt_ref clock output from Core

* Feature Enhancement: CR fixes

* Feature Enhancement: added 25G support for UltraScale+ -1 and -1L speed grades

* Feature Enhancement: Updated RSFEC hierarchy

* Feature Enhancement: Added new Zynq UltraScale+ devices.

* Feature Enhancement: Updated for CR

* Revision change in one or more subcores

1G/2.5G Ethernet PCS/PMA or SGMII (16.0)

* Version 16.0 (Rev. 2)

* Parameter added InstantiateBitslice0 for Native Mode LVDS Solution.

* Port updates in Native mode LVDS Solution to support integration of multiple IP instances seamlessly.

* Multiple reference clock option given for Synchronous SGMII Native Mode LVDS Solution selectable based on Clock Selection parameter.

* Revision change in one or more subcores

32-bit Initiator/Target for PCI (7 Series) (5.0)

* Version 5.0 (Rev. 8)

* No changes

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 13)

* Revision change in one or more subcores

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 12)

* No changes

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 11)

* No changes

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 13)

* General: Rename boolean_vector type definition to permit VHDL-2008 support

* General: Rename USE_DSP generic to TCC_USE_DSPS to avoid clash with Vivado Synthesis use_dsp attribute

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 11)

* No changes

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 12)

* General: Rename boolean_vector type definition to permit VHDL-2008 support

40G/50G Ethernet Subsystem (2.1)

* Version 2.1

* Feature Enhancement: CR

* Feature Enhancement: 50g support for UltraScale+ -1 and -1L speed grades added

* Revision change in one or more subcores

64-bit Initiator/Target for PCI (7 Series) (5.0)

* Version 5.0 (Rev. 8)

* No changes

7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 6)

* Bug Fix: When ChipScope is enabled, userrdy is made an input, the userrdy to GT channel primitive is now asserted only if both the input and signal from resetfsm are asserted: AR68829

* Feature Enhancement: Maximum Line rate increased to 10.3125 gbps for XC7K70TFBG484 and XC7K70TFBV484 devices

* Feature Enhancement: Maximum Line rate increased to 10.3125 gbps for XC7K160TFBG484 and XC7K160TFBV484 devices

* Feature Enhancement: Maximum Line rate increased to 10.3125 gbps for XC7K160TIFBG484 and XC7K160TIFBV484 devices

* Other: Dont touch attribute added for GTZ based design devices: AR67714

7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 4)

* Bug Fix: Removed unwanted display messages

* Bug Fix: Removed option to select 250Mhz of UserClk_freq (AXI Interface Frequency) for the devices xc7z015,xc7z15i and xc7z12s since the timing does not meet

* Feature Enhancement: Added JTAG debugger support to debug LTSSM, Reset sequence and Rx detect sequence. User option is added in the 'Add.Debug Options' GUI page

* Revision change in one or more subcores

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 10)

* General: Updated example design subcore version. No Functional changes

AXI 1G/2.5G Ethernet Subsystem (7.0)

* Version 7.0 (Rev. 8)

* General: Refer to tri_mode_ethernet_mac v9.0 and gig_ethernet_pcs_pma v16_0 core change logs for changes in the sub cores of this core.

* General: Added support for AXI buffer for 2.5G Line Rate for UltraScale devices for 1000Base-X mode and SGMII mode without 1588

* General: Added ports when in shared logic of Asynchronous LVDS solution to support connection of multiple instances of IP seamlessly

* General: Added option to generate MII interface without IO logic

* Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 10)

* General: Updated example design subcore version. No Functional changes

AXI AMM Bridge (1.0)

* Version 1.0 (Rev. 2)

* General: Example design updated to work with invalid address scenario

* Revision change in one or more subcores

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 10)

* General: Bug fix for incorrect detection of APB Ready signal

* General: Updated example design subcore version.

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 11)

* General: Internal device family change, no functional changes

* Revision change in one or more subcores

AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0 (Rev. 2)

* Bug Fix: Update ATS/PRI specific interface definition in Block Design (IPI) Flow

* Bug Fix: Fixed Link Control Register Offset in Example Design's Testbench

* Feature Enhancement: Added JTAG & IBERT debugger support. Debug Options GUI page to debug LTSSM

* Feature Enhancement: Added option to select PM_L23_Entry

* Feature Enhancement: Added no_slv_err parameter to return AXI OK response with data equal to FFFF_FFFF when bus-walking non-existent devices for AXI Master that's unable to process Slave Error response. Apply to RP only

* Other: Change RP Function Number to 0 in Example Design's Testbench

* Revision change in one or more subcores

AXI CAN (5.0)

* Version 5.0 (Rev. 15)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 12)

* Feature Enhancement: DRE feature now supported for data widths of 128, 256 and 512

* Other: Updated example design subcore version.

* Revision change in one or more subcores

AXI Chip2Chip Bridge (4.3)

* Version 4.3

* Bug Fix: Reset sequence update for better timing in SelectIO mode.

* Bug Fix: Improved GUI speed and responsiveness

* Feature Enhancement: Support for ID width up to 24

* Revision change in one or more subcores

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 11)

* Sub core IP clk_wiz version changed to 5.4

* Assigned register initial states to avoid X handshake outputs during simulation.

* Revision change in one or more subcores

AXI Crossbar (2.1)

* Version 2.1 (Rev. 13)

* Sub core IP clk_wiz version changed to 5.4

* Assigned register initial states to avoid X handshake outputs during simulation.

* Revision change in one or more subcores

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 11)

* Sub core IP clk_wiz version changed to 5.4

* Assigned register initial states to avoid X handshake outputs during simulation.

* Revision change in one or more subcores

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 12)

* Sub core IP clk_wiz version changed to 5.4

* Assigned register initial states to avoid X handshake outputs during simulation.

* Revision change in one or more subcores

AXI DataMover (5.1)

* Version 5.1 (Rev. 14)

* General: Enhanced support for IP Integrator

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 13)

* Feature Enhancement: DRE feature now supported for data widths up to 512

* Other: Enhanced support for IP Integrator

* Other: Updated example design subcore version.

* Revision change in one or more subcores

AXI EMC (3.0)

* Version 3.0 (Rev. 12)

* General: Updates to example design. No Functional changes

* Revision change in one or more subcores

AXI EPC (2.0)

* Version 2.0 (Rev. 15)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 15)

* Reversal of bits in Register PCS PMA TEMAC Status Register (0x0000_0030) corrected

* Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 10)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI GPIO (2.0)

* Version 2.0 (Rev. 14)

* Feature Enhancement: Register read option enabled for output data registers

* Other: SW access added to GPIO output data registers.

* Other: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI HWICAP (3.0)

* Version 3.0 (Rev. 16)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI IIC (2.0)

* Version 2.0 (Rev. 15)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Interconnect (2.1)

* Version 2.1 (Rev. 13)

* Update IP Integrator metadata on aclk port to improve IP Integrator connection automation.

* Revision change in one or more subcores

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 9)

* No changes

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 10)

* Sub core IP clk_wiz version changed to 5.4

* Assigned register initial states to avoid X handshake outputs during simulation.

* Revision change in one or more subcores

AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Memory Mapped To PCI Express (2.8)

* Version 2.8 (Rev. 4)

* Bug Fix: PIPE Simulation support added for internal clocking option.

* Bug Fix: Added create_generated_clock constraint for GT's CLKRSVD pin

* Feature Enhancement: Added JTAG debugger support in the Add. Debug Options GUI page to debug LTSSM, Reset sequence and Rx detect sequence.

* Other: Change RP Function Number to 0 in Example Design's Testbench

* Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 11)

* Revision change in one or more subcores

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 14)

* General: XDC updates

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Protocol Checker (1.1)

* Version 1.1 (Rev. 13)

* Bug Fix: pc_status[32] AXI_ERRS_BRESP_AW triggers as soon as BVALID is asserted instead of also waiting for BREADY.

* Bug Fix: pc_status[58] AXI_ERRS_RDATA_NUM triggers as soon as RVALID is asserted instead of also waiting for RREADY.

* New Feature: Added timeout checks against the next expected assertion of each VALID handshake output.

* New Feature: Added LIGHT_WEIGHT mode to reduce synthesis utilization.

* New Feature: Added AXI4Lite status interface.

* New Feature: Added ID value keying to read and write transaction CAMs to prevent excessive logic for high ID_WIDTH.

* Other: Sub core IP clk_wiz version changed to 5.4

* Other: Updated assertion message text to refer to current spec version.

* Revision change in one or more subcores

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 12)

* Sub core IP clk_wiz version changed to 5.4

* Assigned register initial states to avoid X handshake outputs during simulation.

* Revision change in one or more subcores

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 11)

* General: Updated example design subcore version.

* General: The behavior of slave select corrected for auto mode.

* General: UltraScale STARTUPE3 constraints are now part of IP XDC

* Revision change in one or more subcores

AXI Register Slice (2.1)

* Version 2.1 (Rev. 12)

* Sub core IP clk_wiz version changed to 5.4

* Assigned register initial states to avoid X handshake outputs during simulation.

* Revision change in one or more subcores

AXI SmartConnect (1.0)

* Version 1.0 (Rev. 4)

* Resolved various bugs.

* Revision change in one or more subcores

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 16)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 4)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Timer (2.0)

* Version 2.0 (Rev. 14)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Traffic Generator (2.0)

* Version 2.0 (Rev. 13)

* Feature Enhancement: IP updated to support 32 bit ID width for s_axi interface

* Other: IP updated to support 32 bit ID width for s_axi interface

* Revision change in one or more subcores

AXI UART16550 (2.0)

* Version 2.0 (Rev. 14)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 13)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Uartlite (2.0)

* Version 2.0 (Rev. 16)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Verification IP (1.0)

* Version 1.0 (Rev. 1)

* production release

* Revision change in one or more subcores

AXI Video Direct Memory Access (6.3)

* Version 6.3

* General: Enhanced support for IP Integrator

* General: Updated some of the hidden parameter names. The names have been made more meaningful.

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 14)

* Revision change in one or more subcores

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 9)

* General: Internal device family change, no functional changes

* Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 11)

* Revision change in one or more subcores

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 12)

* Revision change in one or more subcores

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 13)

* Updated XDC in sync with FIFO changes

* Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 11)

* Revision change in one or more subcores

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 13)

* Updated XDC ttcl in sync with FIFO changes

* Updated CDC logic to remove combinatorial path.

* Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 11)

* Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 13)

* Update IP integrator metadata for clock port of control register interface to improve make_bd_external automation.

* Update IP integrator metadata for aclk port to improve IP integrator connection automation.

* Revision change in one or more subcores

AXI4-Stream Protocol Checker (1.1)

* Version 1.1 (Rev. 12)

* Revision change in one or more subcores

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 12)

* Revision change in one or more subcores

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 12)

* Revision change in one or more subcores

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 12)

* Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 6)

* New Feature: Added pixel repetition support

* New Feature: Added pixel remapping for YUV420 support

* Revision change in one or more subcores

Accumulator (12.0)

* Version 12.0 (Rev. 10)

* No changes

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 10)

* No changes

Aurora 64B66B (11.2)

* Version 11.2

* New Feature: US GT Wizard Instance can be brought out of Aurora IP for UltraScale devices

* Other: gt_powergood from US GT Wizard is made an output port on Aurora core when GT is inside Aurora IP

* Other: gt_powergood from US GT Wizard is brought to GT wrapper in example design when the GT is in example design, outside Aurora IP

* Revision change in one or more subcores

Aurora 8B10B (11.1)

* Version 11.1

* New Feature: US GT Wizard Instance can be brought out of Aurora IP for UltraScale devices

* Other: gt_powergood from US GT Wizard is made an output port on Aurora core when GT is inside Aurora IP

* Other: gt_powergood from US GT Wizard is brought to gt wrapper in example design when the GT is in example design, outside Aurora IP

* Revision change in one or more subcores

Binary Counter (12.0)

* Version 12.0 (Rev. 10)

* No changes

Block Memory Generator (8.3)

* Version 8.3 (Rev. 6)

* General: Internal device family change, no functional changes

* General: When common_clock is selected, clkb is internally connected to clka, but the interface remains the same to support the backward compatibility. Make sure to connect both of the clocks to the same clock source when in common_clock mode

CANFD (1.0)

* Version 1.0 (Rev. 5)

* General: Updated example design subcore version, no functional changes

* Revision change in one or more subcores

CIC Compiler (4.0)

* Version 4.0 (Rev. 11)

* No changes

CORDIC (6.0)

* Version 6.0 (Rev. 11)

* No changes

CPRI (8.7)

* Version 8.7 (Rev. 2)

* Port Change: Routed stat_rx_delay_value from the FEC to the core output to support more accurate calculation of latency through the FEC.

* Bug Fix: Fixed issue in 64-bit cores where the received Ethernet preamble was corrupted.

* Bug Fix: Synchronized the TX start and end codes to the TX header.

* Bug Fix: Corrected the transceiver timing constraints for UltraScale 9.8Gbps capable cores that use the CPLL at 9.8Gbps.

* Bug Fix: Fixed the 8b10b descrambler for 24.33024Gbps capable cores.

* Bug Fix: Fixed issue where the GT reset block could go into a hang up state if PLL lock is lost after a complete reset sequence.

* Bug Fix: Instantiated the FEC as a dynamic hierarchical sub-core to fix phantom FEC license Critical Warnings.

* Other: Added support for Zynq UltraScale+ RFSoC devices.

* Other: Transceivers on UltraScale and UltraScale+ -2LV speed grade parts changed to use QPLL at 9.8304Gbps.

* Other: Added support for 24.33024Gbps line rate on UltraScale+ (GTYE4) -1 speed grade parts.

* Other: Added support for CPLL calibration block on UltraScale+ (GTHE4 & GTYE4) parts.

* Revision change in one or more subcores

Chroma Resampler (4.0)

* Version 4.0 (Rev. 11)

* No changes

Clocking Wizard (5.4)

* Version 5.4

* Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for UltraScale and UltraScale plus devices.

* Other: Added support for new Zynq UltraScale plus devices.

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 12)

* No changes

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 11)

* No changes

Complex Multiplier (6.0)

* Version 6.0 (Rev. 12)

* No changes

Concat (2.1)

* Version 2.1 (Rev. 1)

* Migrate IPs from IPI-specific repository to regular Vivado IP repository

Constant (1.1)

* Version 1.1 (Rev. 3)

* Migrate IPs from IPI-specific repository to regular Vivado IP repository

Convolution Encoder (9.0)

* Version 9.0 (Rev. 11)

* No changes

DDR3 SDRAM (MIG) (1.4)

* Version 1.4

* Bug Fix: (Xilinx Answer 67392) UltraScale and UltraScale+ Memory IP - pulse width violations can occur

* Feature Enhancement: Partial Reconfiguration support

* Feature Enhancement: Enabled ECC support for MicroBlaze MCS

* Feature Enhancement: Self-Refresh and Save-Restore support for RDIMM

* Revision change in one or more subcores

DDR4 SDRAM (MIG) (2.2)

* Version 2.2

* Bug Fix: (Xilinx Answer 67392) UltraScale and UltraScale+ Memory IP - pulse width violations can occur

* Bug Fix: (Xilinx Answer 68236) Upgrading locked IP might fail for select RDIMMs

* Feature Enhancement: 3DS component support

* Feature Enhancement: Partial Reconfiguration support

* Feature Enhancement: Enabled ECC support for MicroBlaze MCS

* Feature Enhancement: Self-Refresh and Save-Restore support for LRDIMM

* Feature Enhancement: DDP wide component supported

* Feature Enhancement: Removed Selection of CS enable/disable from GUI

* Revision change in one or more subcores

DDS Compiler (6.0)

* Version 6.0 (Rev. 13)

* No changes

DMA/Bridge Subsystem for PCI Express (PCIe) (3.1)

* Version 3.1

* Bug Fix: Fixed axi_aresetn output signal driving based on user_reset

* Bug Fix: Added simulation support for 128byte DMA

* Bug Fix: Enabled support for g1x16, g2x16 configurations for -1L, -1LV and -2LV speedgrades for UltraScale Plus device family

* Bug Fix: Removed option to select 250Mhz of UserClk_freq (AXI Interface Frequency) for the devices xc7z015,xc7z15i and xc7z12s since the timing does not meet

* Bug Fix: Removed m_axib_ruser and m_axib_wuser from M_AXI_B interface when AXI Bridge mode is selected, since these signals are not used in this mode. No change in M_AXI_BYPASS interface when DMA mode is selected

* Feature Enhancement: Added support for xczu7ev device

* Feature Enhancement: Added support for xczu21dr, xczu25dr, xczu28dr and xczu29dr devices

* Feature Enhancement: Added JTAG debugger support in the Add. Debug Options GUI page to debug LTSSM, Reset sequence and Rx detect sequence.

* Feature Enhancement: Added In-System IBERT support in the Add. Debug Options page to scan eye diagram of the serial lane

* Feature Enhancement: Added support for zynquplus devices - xczu4cg,xczu4eg, xczu5cg, xczu5eg, xczu7cg and xczu7eg

* Feature Enhancement: Enabled g3x16 support for all the UltraScale Plus devices and packages for -2L speedgrades

* Feature Enhancement: Removed g3x16 and g3x8 option for -1 speedgrade for all the UltraScale Plus devices and packages

* Feature Enhancement: For all the UltraScale Plus devices and packages, Removed the option to select the coreclock frequency. It is always set to 500MHz now.

* Feature Enhancement: Added support for external GT DRP interface

* Feature Enhancement: Added option to enable PM_L23_Entry

* Feature Enhancement: Added GT Wizard support for Xilinx example design in the Shared Logic page.

* Feature Enhancement: Added Tandem support for vu3p, vu9p, and vu13p.

* Feature Enhancement: Change the default value of User Interrupt Enable Mask in IRQ Block register to always allow interrupt after reset when Bridge functional mode is selected.

* Revision change in one or more subcores

DSP48 Macro (3.0)

* Version 3.0 (Rev. 14)

* General: Improve GUI memory usage

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 11)

* No changes

Debug Bridge (2.0)

* Version 2.0

* Enhanced Debug Bridge IP to support PCIE based XVC solution and reduced the BSCANID vector to single enable pin for reduction number of pins crossing PR boundary.

* Added BSCAN interface definition for Debug Bridge IP

* Revision change in one or more subcores

Decapsulator (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: decap user logic back2back reading on 0xD0 get previous reg read value.

* Bug Fix: decap media_header register reserved bit x change to 0.

* Bug Fix: Changed supported families to discontinued. This IP will no longer available from 2017.2

* Revision change in one or more subcores

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 13)

* Worked around LSB mismatch for point sizes 768 and 1080 between C model and IP seen when simulating with Vivado Simulator or Cadence IES

* Fixed bug in Matlab MEX wrapper which prevented simulation of 1536-point DFT

DisplayPort (7.0)

* Version 7.0 (Rev. 4)

* Bug Fix: Tx RB reset requirement as per FIFO gen

* Bug Fix: HDCP Reset Control

* Feature Enhancement: Add Training Timeout Override

* Feature Enhancement: Support Multiple Block EDID (>256 Bytes)

* Revision change in one or more subcores

DisplayPort RX Subsystem (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: In native mode, GUI will not allow pixel mode greater than lane count

* Bug Fix: Cleaned up INFO messages in subsystem generation

* Feature Enhancement: Gray out HDCP option, if HDCP license is not found

* Revision change in one or more subcores

DisplayPort TX Subsystem (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: In native mode, GUI will not allow pixel mode greater than lane count

* Bug Fix: Cleaned up INFO messages in subsystem generation

* Feature Enhancement: Gray out HDCP option, if HDCP license is not found

* Revision change in one or more subcores

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 11)

* No changes

Divider Generator (5.1)

* Version 5.1 (Rev. 11)

* No changes

Double Data Rate Sampling (1.0)

* Version 1.0

* No changes

ECC (2.0)

* Version 2.0 (Rev. 12)

* No changes

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 14)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

FIFO Generator (13.1)

* Version 13.1 (Rev. 4)

* Bug Fix: FIFO Generator core was constructing the built-in FIFO sub-optimally for 2K-deep and 36-bit wide configuration. This is corrected to use the optimal FIFO structure

* Bug Fix: In order to enable the tool to perform the recovery check on the reset, set_false_path for reset is kept only from the input port to the first flop that it connects to

* Feature Enhancement: Updated the FIFO Generator's constraints to improve tool performance processing its XDC

* Other: Internal device family change, no functional changes

* Revision change in one or more subcores

FIR Compiler (7.2)

* Version 7.2 (Rev. 8)

* Bug Fix: Output Rounding Mode parameter validation corrected to produce an error during design validation (IP Integrator/System Generator) rather than silently updating to a legal value.

* Bug Fix: Correction to Convergent Rounding when multiple DSP slices are required to implement the filter multiply operations.

Fast Fourier Transform (9.0)

* Version 9.0 (Rev. 12)

* General: Bugfix for incorrect Pipelined, Streaming I/O architecture overflow output. Due to the nature of the streaming dataflow, the final value of overflow is only guaranteed on the last cycle of data output.

* General: Cleaned up C model MEX compilation warnings and added option to use -DNO_WARNINGS to mute warnings regarding real-only input data.

* General: Clock frequency improvement for fixed-point Pipelined, Streaming I/O architecture by utilizing write-first BRAM mode. No change in functionality.

* General: Bugfix for incorrect automatic architecture selection when only point size changed on GUI prior to generation.

* General: Bugfix in C model to resolve incorrect output from Windows model when using large input or phase factor widths.

Fiber Channel 32GFC RS-FEC (1.0)

* Version 1.0 (Rev. 2)

* General: Added support for all known control block-type fields to transcoder.

* General: Added support for Zynq UltraScale+ RFSoC devices.

* General: Added support for UltraScale+ devices with -1 and -1L speed grade.

* General: Migrated FIFOs in example design to XPM.

* General: Added explicit initialization for internal TX registers.

* Revision change in one or more subcores

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 8)

* No changes

FlexO 100G RS-FEC (1.0)

* Version 1.0 (Rev. 2)

* General: Added support for Zynq UltraScale+ RFSoC devices.

* General: Added bus definitions for data input and output ports.

* Revision change in one or more subcores

Floating-point (7.1)

* Version 7.1 (Rev. 4)

* General: Corrected fixed-to-float conversion options to avoid illegal configurations in which the fixed-point number range was too large to allow all values to be represented by the half precision exponent.

Framer (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: framer user logic back2back reading on channel space register may get previous reg read value.

* Bug Fix: Changed supported families to discontinued. This IP will no longer available from 2017.2

G.709 FEC Encoder/Decoder (2.3)

* Version 2.3

* Other: Removal of support for Zynq UltraScale Plus -1 speedgrade as speedfiles have matured.

* Unknown category bug fixes: Addition of reset to AXI Lite interface handshake signals.

* Revision change in one or more subcores

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 13)

* No changes

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 14)

* General: Rename boolean_vector type definition to permit VHDL-2008 support

Gamma Correction (7.0)

* Version 7.0 (Rev. 12)

* No changes

GMII to RGMII (4.0)

* Version 4.0 (Rev. 4)

* Bug Fix: Fix for BUFR along with BUFG combination is used in the RX_CLK path

* Bug Fix: Added component name to constraint name

* Bug Fix: Constraint modification for master clock for gmii_tx_clk not being found for some designs

HDCP (1.0)

* Version 1.0 (Rev. 2)

* Fixed CR 956898 - XDC issue

HDCP 2.2 Cipher (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: Fixed cipher synchronization problem for low resolution video caused by clock enable.

HDCP 2.2 Montgomery Modular Multiplier (1.0)

* Version 1.0 (Rev. 1)

* General: Added additional pipelining to improve critical path

HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes

HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDMI 1.4/2.0 Receiver (2.0)

* Version 1.1

* No changes

HDMI 1.4/2.0 Receiver Subsystem (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: Fix for DDC Segment pointer reset issue in HDMI RX core

* Bug Fix: Fix for C_DDC_EDID_SIZE propagation from GUI to HDMI RX core

* Bug Fix: HDCP RX Compliance Fixes for 2017.1 (HDMI Mode detection, Sync Loss Detection, OESS Signaling Support)

* Bug Fix: Fixed CDC issues

* Bug Fix: Reduce BRAM usage in Example design to 512K with HDCP or 256K without HDCP

* Bug Fix: Tie vid_phy_controller input pins vid_phy_tx_axi4s_aresetn and vid_phy_tx_axi4s_aresetn to HIGH

* Bug Fix: Suppress BD warnings by using connect_bd_net -quiet

* Bug Fix: Remove MicroBlaze cache settings from Example design as those are disabled parameters

* Bug Fix: Improve CPU SS reset mechanism

* Feature Enhancement: Example design supporting core upversion (clk_wiz from 5.3 to 5.4, MicroBlaze from 9.6 to 10.0)

* Feature Enhancement: Integrated HLS based remapper feature into video bridge subcore

HDMI 1.4/2.0 Transmitter (2.0)

* Version 1.1

* No changes

HDMI 1.4/2.0 Transmitter Subsystem (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: Fixed running disparity issue in HDMI TX TMDS encoder module to pass 7-16, 7-17, HF1-12 compliance tests

* Bug Fix: Fixed scrambler synchronization issue

* Bug Fix: Fixed Audio instability issue while sending low resolution video

* Bug Fix: Fixed CDC issues

* Bug Fix: Reduce BRAM usage in Example design to 512K with HDCP or 256K without HDCP

* Bug Fix: Tie vid_phy_controller input pins vid_phy_tx_axi4s_aresetn and vid_phy_tx_axi4s_aresetn to HIGH

* Bug Fix: Suppress BD warnings by using connect_bd_net -quiet

* Bug Fix: Remove MicroBlaze cache settings from Example design as those are disabled parameters

* Bug Fix: Improve CPU SS reset mechanism

* Feature Enhancement: Example design supporting core upversion (clk_wiz from 5.3 to 5.4, MicroBlaze from 9.6 to 10.0)

* Feature Enhancement: Integrated HLS based remapper feature into video bridge subcore

High Speed SelectIO Wizard (3.2)

* Version 3.2

* Port Change: New ports introduced Asynchronous Mode support and to enable Multi interface connections

* Bug Fix: Fixed issue in example design simulation when Advanced Strobe option is enabled

* New Feature: Added 3-state option for Tx pins

* New Feature: Added option to generate the required ports to connect multiple interfaces

* New Feature: HASH(0x1dda960)

* Feature Enhancement: Updated support for Asynchronous Mode (Beta)

* Other: For UltraScale Plus devices, with -2LV speed grade, the supported data speed is limited to 1400Mbps for Serialization Factor =4

* Other: Modified the max DELAY VALUE for UltraScale Plus devices to 1100ps

* Other: Added additional synchronizing register to reset input

* Other: DELAY VALUE attribute is modified to be 0ps when OUTPUT_PHASE_90 attribute is set to true

* Other: TX BITSLICE DELAY VALUE is set to 0ps as default in GUI

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 16)

* Revision change in one or more subcores

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 15)

* Revision change in one or more subcores

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 16)

* Changed default value of RXDFEXYDEN to 1.

* Revision change in one or more subcores

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 12)

* No changes

IBERT UltraScale GTH (1.3)

* Version 1.3 (Rev. 6)

* Updated supported device list.

* Added advance settings feature.

* Revision change in one or more subcores

IBERT UltraScale GTY (1.2)

* Version 1.2 (Rev. 6)

* Added advance settings feature.

* Revision change in one or more subcores

IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 4)

* General: Added support for Zynq UltraScale+ RFSoC devices.

* General: Added support for UltraScale+ devices with -1 and -1L speed grade.

* General: Fixed a corner case in sampling of control signals when reset is released.

* Revision change in one or more subcores

IEEE 802.3 50G RS-FEC (1.0)

* Version 1.0 (Rev. 4)

* General: Added support for Zynq UltraScale+ RFSoC devices.

* General: Added support for UltraScale+ devices with -1 and -1L speed grade.

* General: Internal improvements to enhance timing.

* General: Fixed a corner case in sampling of control signals when reset is released.

* Revision change in one or more subcores

IEEE 802.3bj 100G RS-FEC (1.0)

* Version 1.0 (Rev. 8)

* General: Added support for Zynq UltraScale+ RFSoC devices.

* General: Added support for UltraScale+ devices with -1 and -1L speed grade.

* General: Fixed a corner case in sampling of control signals when reset is released.

* Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2 (Rev. 2)

* Updated ILA and Debug Hub IPs to handle CDC warnings

* Revision change in one or more subcores

IOModule (3.1)

* Version 3.1

* Port Change: Added triple modular redundant voting signals

* Feature Enhancement: Support use in a triple modular redundant subsystem

Image Enhancement (8.0)

* Version 8.0 (Rev. 12)

* No changes

In System IBERT (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

Interlaken 150G (2.1)

* Version 2.1

* Port Change: gt_refclk_out port added when shared logic is inside the core configurations

* Feature Enhancement: CR fixes

* Feature Enhancement: Zynq UltraScale plus RFSoC support added

* Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 10)

* No changes

JESD204 (7.1)

* Version 7.1 (Rev. 2)

* General: Added support for UltraScale RF SoC

* General: Removed duplicate bus interfaces in core meta data

* Revision change in one or more subcores

JESD204 PHY (3.3)

* Version 3.3

* Feature Enhancement: Added support for UltraScale RFSoC.

* Feature Enhancement: For 64-bit interfaces only. The clock IO for the core has been revised.

* Feature Enhancement: For 64-bit interfaces only. The port gt_prbssel has been removed.

* Feature Enhancement: For 64-bit interfaces only. The transceiver type supported has been reduced to GTYE3 and GTYE4.

* Revision change in one or more subcores

JESD204C (1.0)

* Version 1.0

* Initial Release

JTAG to AXI Master (1.2)

* Version 1.2 (Rev. 2)

* Updated logic to fix issues related to xsdb reset while opening a hw_target for the second time where read txn data is corrupted

* Revision change in one or more subcores

LPDDR3 SDRAM (MIG) (1.0)

* Version 1.0

* Feature Enhancement: New IP

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 12)

* General: Rename boolean_vector type definition to permit VHDL-2008 support

* Revision change in one or more subcores

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 13)

* General: Add option to use DSP48s for butterflies for increased clock frequency performance with wide datapaths. Default option is still to use LUTs.

* General: Improved achievable clock frequency when using Pipelined, Streaming I/O architecture by utilizing write-first BRAM mode. No functional changes.

* Revision change in one or more subcores

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 11)

* No changes

LTE RACH Detector (3.0)

* Version 3.0

* General: Added support for 1536 point output

* General: Added support for 15, 3 and 1.4 MHz frequency

* General: Per antenna correlation output port added

* General: Interfaces converted to be AXI-S compliant.

* General: C-model made bit accurate to core.

* Revision change in one or more subcores

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 12)

* Bug Fix: Fixed issue where m_axi_wvalid assertion was waiting on m_axi_wready to occur. AR68518

* Bug Fix: Rename boolean_vector type definition to permit VHDL-2008 support

* Revision change in one or more subcores

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 9)

* No changes

MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores

MIPI CSI-2 Rx Subsystem (2.2)

* Version 2.2

* Port Change: Removed system_rst_in port due to system_rst_in removal from MIPI D-PHY

* New Feature: Fsync(TUSER[0]) generation on Embedded non-image interface added

* New Feature: GUI option to filter user defined data type packets on image interface

* Other: High-Speed SelectIO v3.2 IP integration

* Revision change in one or more subcores

MIPI CSI-2 Tx Controller (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

MIPI CSI-2 Tx Subsystem (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Fixed the scenario when the Word-Count > Received Payload to safely process the packet

* Bug Fix: Fixed the Clock Lane Enable & Request resetting w.r.t Controller Reset

* Feature Enhancement: Updated 7 Series line rates

* Revision change in one or more subcores

MIPI D-PHY (3.1)

* Version 3.1

* Port Change: Removed system_rst_in port from D-PHY RX IP configuration (See Product Guide PG202 "Port Descriptions" section for list of the ports.)

* Bug Fix: Removed system_rst_in port from D-PHY RX IP configuration

* Bug Fix: Added FIFO_RD_EN_CONTROL parameter of HSSIO IP sub-core in UltraScale+ D-PHY RX IP configuration

* Bug Fix: Implemented T_WAKEUP timing parameter for D-PHY RX IP configuration

* Bug Fix: Added parameter to control HS_SETTLE timing parameter for D-PHY RX IP configuration

* Bug Fix: Updated 7 Series line rates

* Bug Fix: Added C_EN_HS_OBUFTDS parameter to control OBUFTDS instantiation for 7 Series D-PHY TX IP

* Bug Fix: Added C_INIT parameter to control T_INIT timing parameter

* Bug Fix: Updated default value of T_INIT parameter for D-PHY RX (slave) IP configuration from 500000 ns to 100000 ns

* Bug Fix: Fixed auto calibration mode data ordering for multi-lane 7 Series D-PHY RX (slave) IP configuration

* Other: High-Speed SelectIO v3.2 IP integration

* Other: Clocking Wizard v5.4 IP integration

MIPI DSI Tx Controller (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores

MIPI DSI Tx Subsystem (1.1)

* Version 1.1 (Rev. 2)

* Feature Enhancement: Updated 7 Series line rates

* Revision change in one or more subcores

Mailbox (2.1)

* Version 2.1 (Rev. 7)

* No changes

Memory Helper Core (1.4)

* Version 1.4

* Support for Vivado 2017.1

Memory Interface Generator (MIG 7 Series) (4.0)

* Version 4.0 (Rev. 3)

* General: Vivado 2017.1 software support.

MicroBlaze (10.0)

* Version 10.0 (Rev. 2)

* Bug Fix: Prevent inadvertent setting of the MSR Break In Progress (BIP) flag when a software breakpoint occurs. Versions that have this issue: 10.0. Can only occur with the frequency optimized 8-stage pipeline when using software breakpoints in the debugger.

* Feature Enhancement: Support extended address using MMU physical address extension (PAE)

* Feature Enhancement: Allow setting external program trace buffer size

* Other: Added support for Zynq UltraScale+ RFSOC and Virtex UltraScale+ HBM devices

* Other: Updated logotype

* Other: Simplified decoding of extended debug program trace

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 9)

* Bug Fix: Corrected step into behavior on UltraScale+

* Bug Fix: Added BSCAN timing constraint to ensure MicroBlaze is detected on UltraScale+

* Feature Enhancement: Allow setting data width for AXI-Stream external trace

* Feature Enhancement: Provide parameter to control instantiation of primitives

* Feature Enhancement: Support parallel debug interface via BSCAN when debug register access from AXI is not enabled

MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 4)

* General: Updated with latest subcore versions

* General: Added logotype

* Revision change in one or more subcores

Multiplier (12.0)

* Version 12.0 (Rev. 12)

* No changes

Multiply Adder (3.0)

* Version 3.0 (Rev. 10)

* No changes

Mutex (2.1)

* Version 2.1 (Rev. 8)

* No changes

PCIe PHY IP (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Updated the cpll cal counters as per the frequency of reference clock selected

* Revision change in one or more subcores

Partial Reconfiguration Controller (1.1)

* Version 1.1 (Rev. 2)

* Revision change in one or more subcores

Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 4)

* General: Internal metadata change.

Peak Cancellation Crest Factor Reduction (6.1)

* Version 6.1 (Rev. 1)

* Bug Fix: Added generic to remove unused flops.

* Bug Fix: Optimized DSP48 usage in WCFR when smart peak processing is disabled.

Processor System Reset (5.0)

* Version 5.0 (Rev. 11)

* General: Board flow related updates, no functional changes

QDRII+ SRAM (MIG) (1.4)

* Version 1.4

* Revision change in one or more subcores

QDRIV SRAM (MIG) (2.0)

* Version 2.0

* Revision change in one or more subcores

QDRIV SRAM PHY IP (2.0)

* Version 1.2

* No changes

QSGMII (3.3)

* Version 3.3 (Rev. 8)

* General: Added support for Zynq UltraScale+ DR family

* Revision change in one or more subcores

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 10)

* No changes

RFC3190 De-Packetizer (1.0)

* Version 1.0 (Rev. 1)

* General: Discontinued all supported device families and this IP will not be available from the 2017.2 release on

RFC3190 Packetizer (1.0)

* Version 1.0 (Rev. 1)

* General: Discontinued all supported device families and this IP will not be available from the 2017.2 release on

RFC4175 De-packetizer (1.0)

* Version 1.0 (Rev. 1)

* General: Changed supported_families to discontinued. This IP will not be available from the 2017.2 release on

RFC4175 Packetizer (1.0)

* Version 1.0 (Rev. 1)

* General: Changed supported_families to discontinued. This IP will not be available from the 2017.2 release on

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 10)

* No changes

RLDRAM3 (MIG) (1.4)

* Version 1.4

* Bug Fix: Updated for 2017.1 CRs.

* Feature Enhancement: Added MicroBlaze MCS ECC.

* Revision change in one or more subcores

RXAUI (4.3)

* Version 4.3 (Rev. 8)

* General: Added support for Zynq UltraScale+ DR family

* Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 12)

* No changes

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 11)

* No changes

S/PDIF (2.0)

* Version 2.0 (Rev. 15)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

SC EXIT (1.0)

* Version 1.0 (Rev. 4)

* Change auto family support level

SC MMU (1.0)

* Version 1.0 (Rev. 4)

* Change auto family support level

SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 4)

* Change auto family support level

SC SPLITTER (1.0)

* Version 1.0 (Rev. 2)

* No changes

SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 4)

* Change auto family support level

SMPTE 2022-1/2 Video over IP Receiver (2.0)

* Version 2.0 (Rev. 9)

* Bug Fix: fixed bug, where prot_lvl register bit was not getting updated when switched from levelA to levelB. This bug only affects register value update, has no impact on core function

* Bug Fix: Changed supported_families to discontinued. This IP will no longer be available from 2017.2

* Revision change in one or more subcores

SMPTE 2022-1/2 Video over IP Transmitter (2.0)

* Version 2.0 (Rev. 9)

* General: Changed supported_families to discontinued. This IP will no longer be available from 2017.2

* Revision change in one or more subcores

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 8)

* No changes

SMPTE ST 2059 (1.0)

* Version 1.0 (Rev. 2)

* General: Changed supported_families to discontinued. This IP will no longer be available from 2017.2

SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Added xyz checking logic for mode lock assertion.

* Bug Fix: Added core XDC constraint for Tx EDH logic

SMPTE2022-5/6 Video over IP Receiver (5.0)

* Version 5.0 (Rev. 8)

* General: Discontinued all supported device families and this IP is no be available from 2017.2

* Revision change in one or more subcores

SMPTE2022-5/6 Video over IP Transmitter (4.0)

* Version 4.0 (Rev. 10)

* General: Discontinued all supported device families and this IP is no longer be available from 2017.2

* Revision change in one or more subcores

SPI-4.2 (13.0)

* Version 13.0 (Rev. 10)

* Repackaged demo testbench glbl.v file

ST2022-56 De-Packetizer (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Changed supported families to discontinued. This IP will no longer available from 2017.2

* Other: Fix in demo_tb for FIFO generator

ST2022-56 Packetizer (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Changed supported families to discontinued. This IP will no longer available in 2017.2

* Other: Fix in demo_tb for FIFO generator usage

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 9)

* Bug Fix: Fixed the generation of ref_clk and delay_locked ports in IPI when IDELAYCTRL is deselected

Serial RapidIO Gen2 (4.0)

* Version 4.0 (Rev. 7)

* Feature Enhancement: Added support for Zynq UltraScale+ MPSoC CG family & EG extension devices

* Revision change in one or more subcores

SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 4)

* Change auto family support level

SmartConnect Node (1.0)

* Version 1.0 (Rev. 4)

* Remove FIFO Generator references

SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 4)

* Change auto family support level

SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 4)

* Change auto family support level

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 8)

* General: Add Pre-production support for new devices XC7S6, XC7S15, XC7S75, XC7S100 (not verified in hardware)

System Cache (4.0)

* Version 4.0 (Rev. 2)

* Bug Fix: Fixed issue with Read Allocate override parameter that could corrupt Read response

* Other: Added support for Zynq UltraScale+ RFSOC and Virtex UltraScale+ HBM devices

* Other: Removed unused source file

System ILA (1.0)

* Version 1.0 (Rev. 2)

* Added axi4 transaction tracking feature

* Revision change in one or more subcores

System Management Wizard (1.3)

* Version 1.3 (Rev. 4)

* General: Internal GUI Updates.

* General: Temperature_Enable bit is now obsolete. User need not write this bit to 1 if temp_bus is enabled.

TMR Comparator (1.0)

* Version 1.0

* General: Initial Vivado release

TMR Inject (1.0)

* Version 1.0

* General: Initial Vivado release

TMR Manager (1.0)

* Version 1.0

* General: Initial Vivado release

TMR Soft Error Mitigation Interface (1.0)

* Version 1.0

* General: Initial Vivado release

TMR Voter (1.0)

* Version 1.0

* General: Initial Vivado release

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 7)

* General: Reduced the length of IP generated file names

* General: Prevent generation of empty text files

UltraScale 100G Ethernet Subsystem (2.1)

* Version 2.1

* Port Change: Added axi_switch_caui_mode output port for runtime switchable with axi4 lite enabled

* Port Change: Added gt_ref_clk_out output port for GT subcore in core

* Port Change: Added ANLT ports when ANLT is enabled

* Feature Enhancement: Added support for GT refclk 156.25MHz and 312.5MHz for CAUI4 line rate

* Feature Enhancement: Added support for optional AN/LT reduced size

* Other: Clocking mode is selected as Asynchronous and greyed out

* Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.3)

* Version 4.3

* Bug Fix: Corrected the order of evaluation of PF0/1_Use_Class_Code_Lookup_Assistant user parameters to avoid the warnings during core generation

* Bug Fix: Fixed issue with the VHDL wrapper generation when the target language is set to VHDL

* Feature Enhancement: JTAG debugger module is moved inside the core top module

* Feature Enhancement: In-System IBERT module is moved inside the core top module and enabled for all link speeds

* Feature Enhancement: Added option to enable PM_L23 Entry in Rootport configuration. Set the user parameter 'Enable PM_L23_Entry' on 'Power Management' tab when Rootport and Advanced mode are selected

* Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.6)

* Version 1.6 (Rev. 6)

* Feature Enhancement: Increased UltraScale+ GTY transceivers line rate for -1/-1L speed grade devices to support up to 25.78125 Gb/s

* Feature Enhancement: Adjusted line rate and associated frequency limits for -1H/-2LV speed grade devices to match the UltraScale+ FPGAs Data Sheet

* Feature Enhancement: Enhanced the choice of GTYE3/GTYE4 Reference clock sharing for line rates greater than 16.375 Gb/s

* Feature Enhancement: Updated the CPLL calibration module for UltraScale+ devices and added a simulation only bypass logic under pragma control

* Other: Updated the transceiver configuration preset options for Interlaken to cover only 1 quad

* Other: When Manual alignment (RXSLIDE) mode is enabled, alignment boundary is now allowed to be selected

* Other: GUI enhancement to allow the line rate to start with a decimal point, earlier this was erroring out

* Other: Fixed a bug in the Wizard customization GUI Physical Resources tab that caused the incorrect column to be displayed for some GTHE4/GTYE4 based devices

* Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 3)

* General: Added support for Zynq UltraScale+ RFSoC devices

* General: Added support for all SSI Virtex UltraScale+ devices. Classification, PEEK commands and diagnostic scan features are not supported.

* General: Updated the maximum ICAP clock frequency for UltraScale+ low voltage devices to 150Mhz

UltraScale+ 100G Ethernet Subsystem (2.2)

* Version 2.2

* Port Change: Added axi_switch_caui_mode output port for runtime switchable with axi4 lite enabled

* Port Change: Added gt_ref_clk_out output port for GT subcore in core

* Port Change: Added ANLT ports when ANLT is enabled

* Port Change: Added TX OTN ctl and stat ports when enabled

* Feature Enhancement: Added support for GT refclk 156.25MHz and 312.5MHz for CAUI4 line rate

* Feature Enhancement: Added IPI Designer Assistance support

* Feature Enhancement: Added support for optional AN/LT reduced size

* Feature Enhancement: Added support Tx OTN Mapping mode option with and without client monitoring

* Feature Enhancement: Added RSFEC support for runtime switchable mode

* Other: Clocking mode is selected as Asynchronous and greyed out

* Other: Virtex UltraScale+ -1/-1L devices support for 25G line rate

* Revision change in one or more subcores

UltraScale+ PCI Express Integrated Block (1.2)

* Version 1.2

* Bug Fix: Fixed issue with the core generation for xczu7ev-fbvb900 device when x16 configuration is selected by enabling valid GT Quads.

* Bug Fix: Fixed SRIOV PF's First VF Offset default value.

* Bug Fix: Fixed SRIOV VF's Next Capability Pointer at PCIe Configuration Space offset 0x34

* Bug Fix: Enable or Disable MSI-X Capability Structure uniformly on all PFs and VFs when SRIOV capability is enabled

* Feature Enhancement: Added support for xczu21dr, xczu25dr, xczu25dr and xczu28dr devices.

* Feature Enhancement: JTAG debugger module is moved inside the core top module.

* Feature Enhancement: In-System IBERT module is moved inside the core top module and enabled for all link speeds.

* Feature Enhancement: Added Tandem and MCAP support for KU15P, VU3P, VU5P, VU7P, VU9P, VU11P, VU13P, and zu19EG

* Feature Enhancement: Added example on VSEC to the example design when extended config is enabled.

* Feature Enhancement: Added GT DRP Arbiter module to support In-System IBERT and user DRP access

* Feature Enhancement: Added free_run_clock option in the GT Settings GUI tab

* Feature Enhancement: Added support for Zynq UltraScale Plus devices - xczu4cg,xczu4eg, xczu5cg, xczu5eg, xczu7cg and xczu7eg

* Feature Enhancement: Updated the tandem with field updates scripts to use the new PR methodology

* Feature Enhancement: Added debug core examples to the tandem with field updates example design.

* Feature Enhancement: Added option to enable PM_L23 Entry in Rootport configuration. Set the user parameter 'Enable PM_L23_Entry' on 'Adv.Options-1' tab when Rootport and Advanced mode are selected

* Feature Enhancement: Added special non-ARI 1PF+7VF SRIOV configuration

* Revision change in one or more subcores

Utility Reduced Logic (2.0)

* Version 2.0 (Rev. 3)

* Migrate IPs from IPI-specific repository to regular Vivado IP repository

Utility Vector Logic (2.0)

* Version 2.0 (Rev. 1)

* Migrate IPs from IPI-specific repository to regular Vivado IP repository

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 15)

* XDC updated for Zynq UltraScale+ devices

* Revision change in one or more subcores

Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 6)

* General: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video Deinterlacer (5.0)

* Version 5.0 (Rev. 6)

* Revision change in one or more subcores

Video Frame Buffer Read (1.0)

* Version 1.0

* First version released

Video Frame Buffer Write (1.0)

* Version 1.0

* First version released

Video Horizontal Chroma Resampler (1.0)

* Version 1.0 (Rev. 6)

* General: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video Horizontal Scaler (1.0)

* Version 1.0 (Rev. 6)

* General: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 6)

* New Feature: Added pixel drop support

* Revision change in one or more subcores

Video Letterbox Engine (1.0)

* Version 1.0 (Rev. 6)

* General: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video Mixer (1.0)

* Version 1.0 (Rev. 4)

* Feature Enhancement: Added support for semi-planar YUV 4:2:2 and YUV 4:2:0

* Feature Enhancement: Added support for BGRA8 and luma-only

* Other: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Other: Memory Mapped AXI4 interface property NUM_READ_OUTSTANDING changed from 2 to 4

* Revision change in one or more subcores

Video On Screen Display (6.0)

* Version 6.0 (Rev. 13)

* No changes

Video PHY Controller (2.0)

* Version 2.0 (Rev. 5)

* Bug Fix: Removed GT Common block instantiation if only CPLL is active for HDMI Applications

* Bug Fix: Added WIDTH_OUT parameter to vid_phy_controller_v2_0_dru to control the output width of the DRU wrapper

* Bug Fix: Change COMMON_CFG 6 to 1 in GTHE2 Common block for Virtex devices for Virtex-7 GTH QPLL Temperature compensation

* Bug Fix: Added component name as prefix to names assigned in create_clocks to avoid conflicts for multiple VPHY instances in same BD

* Bug Fix: Added IS_SEQUENTIAL to set_false_path for DRU control ports to remove warnings

* Bug Fix: Added ERR_IRQ in top level ports which is controlled by register 0x3C. This port is pulsed high if any of the 0x3C bits are asserted during error conditions

Video Processing Subsystem (2.0)

* Version 2.0 (Rev. 4)

* General: GUI update, no functional change

* Revision change in one or more subcores

Video Test Pattern Generator (7.0)

* Version 7.0 (Rev. 6)

* General: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video Timing Controller (6.1)

* Version 6.1 (Rev. 10)

* No changes

Video Vertical Chroma Resampler (1.0)

* Version 1.0 (Rev. 6)

* General: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video Vertical Scaler (1.0)

* Version 1.0 (Rev. 6)

* General: Replaced AXI BFM Core with AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video over IP FEC Receiver (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: Changed supported families to discontinued. This IP will not be available from the 2017.2 release on

* Revision change in one or more subcores

Video over IP FEC Transmitter (2.0)

* Version 2.0 (Rev. 4)

* Bug Fix: Changed supported families to discontinued. This IP will not be available from the 2017.2 release on

* Revision change in one or more subcores

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.2)

* Version 4.2 (Rev. 4)

* Bug Fix: Corrected the order of evaluation of PF0/1_Use_Class_Code_Lookup_Assistant user parameters to avoid the warnings during core generation

* Feature Enhancement: Added JTAG debugger support to debug LTSSM, Reset sequence and Rx detect sequence. User option is added in the 'Add.Debug Options' GUI page

* Revision change in one or more subcores

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 7)

* No changes

XADC Wizard (3.3)

* Version 3.3 (Rev. 3)

* Bug Fix: Fixed the ADC conversion rate calculation.

XAUI (12.2)

* Version 12.2 (Rev. 8)

* Bug Fix: Added extra GT reset control ports gt_reset_tx_pll_and_datapath_in, gt_reset_rx_pll_and_datapath_in, gt_reset_tx_datapath_in and gt_reset_rx_datapath_in

* Bug Fix: Changed value of SYNC_COUNT_LENGTH to 26 for UltraScale devices

* Other: Added support for Zynq UltraScale+ DR family

* Revision change in one or more subcores

XHMC (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Remove value 1 from the validation list for axi4_if_wdt_flit and axi4_if_rdt_flit

* Bug Fix: Change the parameter overwriting mechanism when set isi_in_ip for simulation

* Revision change in one or more subcores

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 10)

* No changes

ZYNQ UltraScale+ VCU (1.0)

* Version 1.0

* Initial release

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 5)

* Zynq BFM is replaced by Zynq VIP

ZYNQ7 Processing System VIP (1.0)

* Version 1.0

* Initial Version

* Using interface AXI VIP

Zynq UltraScale+ MPSoC (3.0)

* Version 3.0

* Multiple changes in interface and signal names for Zynq UltraScale+ MPSoC. As a result of this, upgrade from project prior to 2016.4 may not be complete, requiring re-entry of settings. Please refer to Xilinx Answer 67861 for upgrade details.

* Interface and Signal Name changes

* 1) GEM related: The FIFO_ENET interface associated with the GEM peripheral was packaged incorrectly in prior releases. Interfaces should not have clocks as part of them. Clock signals have been separated from ENET_FIFO interface in this release. In addition to this change, the FIFO_ENET interface is automatically disabled on upgrade. If the design was making use of the interface, reconnect the same.

* 2) GEM related: FIFO_ENET input clocks - fmio_gemx_fifo_tx/rx_clk_from_pl are removed and looped back internally from fifo_tx/rx_clk_to_pl_bufg port.

* 3) GEM related: FIFO_ENET and PTP_ENET related interfaces are not enabled by default for GEM peripherals. In order to enable these, use the PS-PL Configuration (General/Others) in the GUI.

* 4) Inter Processor Interrupts: Interrupts from PS to PL were grouped together as a vector in prior releases. This did not allow for the accurate mapping of the IP Iintegrator channels to respective interrupts. These have now been split into individual interrupt lines. For example, ps_pl_irq_pl_ipi[3;0] in prior releases will now be seen as ps_pl_irq_ipi_channel7 through ps_pl-irq_ipi_channel10. Note that the actual port names will depend on the channel selected in GUI.

* 5) PMU: By default PMU AIB, ACK, PL errors to and from PMU to PL are disabled, separate selection is given under PS - PL Configuration (General/Others) in the GUI.

* Multiple changes in DDR for Zynq UltraScale+ MPSoC as a result some of the UI options are removed and DRCs have been added and modified

* 1) In prior releases, DDR settings such as timing parameters were validated based on the Speed Bin and User Requested Frequency. In the 2017.1 release, the method has been updated to validate based on the actual calculated frequency based on PLL output. This frequency is displayed on the DDR page. The upgrade may fail if your timing value settings do not match the actual frequency computed.

* General Updates

* 1) Isolation Configuration has been improved in 2017.1 release; Refer to PG201 for complete details.

* 2) GPIO: Selection of width for EMIO GPIO is now allowed.

* 3) Zynq UltraScale+ Block diagram has been updated in the GUI to reflect availability of blocks and the correct names for the same.

* 4) Tool Tips have been added to the GUI for usability.

* Additional DRC checks

* 1) GEM_TSU: Through manual mode of clocking, users could cross the limit of 250 Mhz in prior releases. Checks have been added to limit this to the correct range. Upgrade with incorrect frequency will not be successful.

* 2) SD: Checks have been added for the internal DLL used by SD. Violation of requirements will be flagged as a critical warning

axi_sg (4.1)

* Version 4.1 (Rev. 6)

* Revision change in one or more subcores

interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes

lib_bmg (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes

oddr (1.0)

* Version 1.0 of the oddr block.


AR# 69055
Date 04/24/2017
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2017.1
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