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AR# 69143

2017.1-2017.4 Zynq UltraScale+ MPSoC: Connecting XSDB to Linux CPU idle


In the 2017.1-2017.4 release, Linux CPU Idle is enabled by default.

When enabled, Linux powers down the CPU cores when they are idling (as opposed to WFI).

That can cause problems when xsdb is connected.




With CPU Idle enabled, DAP throws out an error. 

In theory, when xsdb is connected, there should be some read/write access happening over the A53_* related registers. 

Because the A53_* cores could be powered down based on the CPU usage stats, due to CPU_IDLE being enabled, the xsdb accesses to the A53 registers can result in a DAP error.

There are two independent events happening here: 

CPUs being powered down and xsdb trying to access the registers. 

As a result, when the xsdb triggers a read, if the A53_* core is powered down, it can result in a DAP error. 

In general, the debugger checks if the block is powered up or not. However, this event might occur when the read is already in progress, and will cause this issue.



The problem can be avoided by disabling the CPU Idle in Linux kernel bootargs using any of the below methods.

1) Disabling from a U-boot prompt on target:

Add "cpuidle.off=1" to bootargs as follows:

ZynqMP> setenv bootargs 'console=ttyPS0,115200n8 earlycon clk_ignore_unused cpuidle.off=1'
ZynqMP> run bootcmd


2) Disable from the kernel config (CONFIG_CPU_IDLE) using PetaLinux or Yocto:

$ petalinux-config -c kernel


$ bitbake -c menuconfig virtual/kernel

CPU Power Management --->
  -> CPU Idle --->
        [ ] CPU idle PM support


3) Using the PetaLinux device-tree generator:

Add the below content to the dtsi file "<plnx- proj- root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi"


/ {
   chosen {
      bootargs = "cpuidle.off=1";


$ petalinux-build -c device-tree

AR# 69143
Date 12/20/2017
Status Active
Type General Article
  • Zynq UltraScale+ MPSoC
  • Vivado Design Suite - 2017.1
  • Vivado Design Suite - 2017.2
  • Linux
  • More
  • Vivado Design Suite - 2017.3
  • Vivado Design Suite - 2017.4
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Boards & Kits
  • Zynq UltraScale+ MPSoC Boards and Kits
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