Version Found: 2017.1
I am using the example design generated by the High Speed SelectIO Wizard with Bus Direction = TX+RX and I am encountering the following error:
Note: this Answer Record should not be viewed in isolation.
For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
The issue only exists with the port mapping in the example design in a small number of instances.
To work around the issue you can comment out the line from the instantiation: