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AR# 69188

High Speed SelectIO Wizard - Incorrect port mapping in example design when using Bus Direction = TX+RX

Description

Version Found: 2017.1

I am using the example design generated by the High Speed SelectIO Wizard with Bus Direction = TX+RX and I am encountering the following error:

ERROR: [VRFC 10-426] cannot find port en_vtc_bsc4 on this module .*/my_ip_ex/imports/my_ip_exdes.v:778]


Note: this Answer Record should not be viewed in isolation. 

For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

Solution

The issue only exists with the port mapping in the example design in a small number of instances.

To work around the issue you can comment out the line from the instantiation:

//    .dly_rdy_bsc4            (exdes_dly_rdy_bsc4),
//    .vtc_rdy_bsc4            (exdes_vtc_rdy_bsc4),
//    .en_vtc_bsc4             (1'b1),
AR# 69188
Date 05/26/2017
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
  • Kintex UltraScale+
  • Kintex UltraScale
  • More
  • Virtex UltraScale+
  • Virtex UltraScale
  • Less
Tools
  • Vivado Design Suite - 2017.1
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