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AR# 69308

UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2017.1) - GT DRP Arbiter Block

Description

Version Found: 4.3

Version Resolved and other Known Issues: (Xilinx Answer 57945)

The tactical patch provided with this answer record adds a GT DRP Arbiter Block to share the DRP interface between multiple modules such as In System IBERT, the Falling Edge Receiver Detect module, EyeScan Reset, and the DFE/LPM Gen3 RX Equalization module.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

This is a known issue to be fixed in a later release of the core.

To fix the issue in Vivado 2017.1, please install the patch attached to this Answer Record as described in the 'patch_readme' directory of the patch attached.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

07/25/2017 - Initial release

Attachments

Associated Attachments

Name File Size File Type
AR69308_Vivado_2017_1_preliminary_rev2.zip 917 KB ZIP
AR# 69308
Date 07/25/2017
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2017.1
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)
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