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AR# 69315

Kintex UltraScale+ FPGA KCU116 Evaluation Kit - Board Debug Checklist

Description

The Kintex UltraScale+ FPGA KCU116 Evaluation Kit Checklist is useful to debug board-related issues and to determine if applying for a Board RMA is the next step.

Before working through the KCU116 Board Debug Checklist, please review (Xilinx Answer 68360) - Kintex UltraScale+ KCU116 Evaluation Kit - Known Issues and Release Notes Master Answer Record, as the issue you are faced with might be covered there.

Solution

 


 

 

Figure 69315-1: KCU116

Table 69315-1: Callouts

 


 

 

 

 

  1. Switch / Jumper Settings
  2. Board Power
  3. Cable detection
  4. JTAG Initialization

The following debug steps assume steps 1-4 have been checked and are working:

  1. JTAG Configuration
  2. Master SPI Configuration
  3. PCIe
  4. IBERT
  5. DDR4
  6. Interface Tests
  7. Known Issues for KCU116


1) Switch / Jumper Settings

Default Switch and Jumper Settings for the KCU116 are:

Start from a known safe scenario by verifying the default Switch and Jumper settings. You can then set switches / jumpers for your application.

a) DIP Switch Default Settings:


 

DIP switches are active-High (connected net is pulled High when DIP switch is closed = 1).


b) DIP Switch SW21 Mode Settings:

Mode pins M1 and M0 are hard wired to logic 0 and 1 respectively.  

Mode pin M2 is wired to SW21 pin 6 (switch position 6), which has the default setting OPEN, enabling the M2 net to be pulled down to logic 0 (e.g., the FPGA default mode setting M[2:0] = 001), selecting the Quad SPI configuration mode.

 


 

 

 

c) Default Jumper Settings:

The Figure below shows the KCU116 board jumper header locations. 

Each numbered component shown in the figure is keyed to the subsequent Table, which identifies the default jumper settings.

 


 

 

 

 


 

 

 
 



2) Board Power
 
Power-ON LEDs: Initial power testing is performed on the bench using the AC-to-DC power adapter provided in the KCU116 Evaluation Kit.

The status of the Power-ON LEDs is an indication of board health.

a) Check the status of the following LEDs at Power-ON:

 





 








b) Ethernet PHY status LEDs.

These LEDs are visible on the left edge of the KCU116 board when it is installed into a PCIe slot in a PC chassis.

 

The two PHY status LEDs are integrated into the metal frame of the P3 RJ-45 connector, as shown below:

 


 

 

c) Voltage and current monitoring, as well as control of the Maxim Integrated power system is available through either the KCU116 System Controller or via the Maxim Integrated PowerTool software graphical user interface.

The KCU116 System Controller is the simplest and most convenient way to monitor the voltage and current values for the power rails on the board. 

More information on the System Controller can be found in (UG1239) KCU116 Board User Guide (https://www.xilinx.com/support/documentation/boards_and_kits/kcu116/ug1239-kcu116-eval-bd.pdf), and also in XTP465 the System Controller Tutorial, available on the KCU116 Product page.

The Maxim Integrated InTune power controllers can also be accessed through the PMBus connector J84.

Using this connector requires the Maxim PowerTool USB cable / dongle (Maxim part number MAXPOWERTOOL002#).

If the Power ON LEDs are not lit at power on, you might need to reprogram the Maxim Integrated Power Controllers on your KCU116.

This can be done using the Maxim Integrated PowerTool software package, and the Maxim Integrated Dongle.

Information on the Maxim Integrated Power Solution on the KCU116 can be found in (Xilinx Answer 69811), together with information on how to order a Maxim Integrated USB cable free of charge.

The Maxim Integrated Power Controllers on the KCU116 can be reprogrammed. This is the first debug work that should be undertaken if power issues are discovered on your KCU116.

Step-by-step instructions, together with the script to be used to reprogram the Maxim devices can be found in (Xilinx Answer 69856).

d) If the 12V power LED (DS2 on the KCU116) is not Green upon power up, and there is not an issue with the LED itself, then 12VDC is not being delivered to the KCU116 power input connector.

Follow these steps:



3) Cable detection

The KCU116 uses a USB A-to-micro-B cable plugged into the KCU116 Digilent USB-to-JTAG module, U21.

A 2-mm JTAG header (J8) is also provided in parallel for access by Xilinx download cables such as the Platform Cable USB II.

a) USB A-to-micro-B cable:

  1. Is the cable visible in Device Manager?
    If the three items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.

  2. Are cable drivers loaded correctly? Drivers for this cable should be included in the Vivado Design Tools installation.
    However, if problems are experienced with USB A-to-micro-B cable connection, a Digilent plug-in can be downloaded from the link below.
    For installation, please follow the guidelines in the document provided in the downloaded files:
    http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN.
    This plug-in requires Adept systems 2.4 or later for Windows and Adept systems 2.3.9 or later for Linux.
    Adept software is available from Digilent:
    http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2.

  3. Check system properties and environment variables.
    For information on environment variables, see (Xilinx Answer 11630).

  4. Is the USB port enabled?
    You can reboot your system to re-initialize the USB buses.

  5. Are Xilinx tools correctly installed? (Vivado Hardware Manager or ILA)
    For supported software version information, see the Kit Product Page:
    https://www.xilinx.com/products/boards-and-kits/ek-u1-kcu116-g.html 
    If an issue is suspected with tools installation, see the Installation and Licensing Guide, (UG973) (make sure to use the most recent version of tools and associated documentation which supports the KCU116).

  6. Is the Operating System (OS) being used Windows 7?
    If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).

b) Platform Cable USB II

  1. Is the cable visible in Device Manager?

  2. Are cable drivers loaded correctly? Drivers for this cable should be included in the Vivado Design Tools installation.
    However, if problems are experienced with the Platform Cable USB II connection, please follow the uninstall and reinstall instructions in (Xilinx Answer 44397).

  3. Check system properties and environment variables.
    For information on environment variables, see (Xilinx Answer 11630).

  4. Is the USB port enabled? You can reboot your system to re-initialize the USB buses.

  5. Are Xilinx tools correctly installed? (Hardware Manager or ILA)
    For supported software version information, see the Kit Product Page:
    https://www.xilinx.com/products/boards-and-kits/ek-u1-kcu116-g.html 
    If an issue is suspected with tools installation, see the Installation and Licensing Guide, UG973 (make sure to use the most recent version of tools and associated documentation which supports the KCU116).

  6. Is the Operating System (OS) being used Windows 7?
    If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).



If the above steps do not enable you to connect, please review the Support Webpage for your available Support options.

 


4) JTAG Initialization

The status of the board JTAG chain is checked using Xilinx Tools (Hardware Manager in Vivado).
To check to see that the JTAG chain is initialized correctly, follow this JTAG Initialization Test Case:

 

  1. Remove any FMC cards from KCU116.
  2. Set the mode switch SW21 for JTAG mode (101).
  3. Power up KCU116 on the bench (not in a PC chassis).
  4. Connect the Digilent USB A-to-micro B cable to the KCU116 (through the Digilent onboard USB-to-JTAG configuration logic module - U21 - through header J2).
  5. Check that the Digilent device shows up in the Device Manager.
  6. Ensure Xilinx tools (Vivado 2017.1 or later - preferably the latest version of tools that support the KCU116) are correctly installed.
  7. Launch Vivado Hardware Manager - is the cable identified correctly? 

 

  • If not, see section 3) Cable detection above.
  • If yes, but Vivado Hardware Manager did not discover and display the JTAG chain, slow down the cable speed (Output > Cable Setup).
  • If yes, but Vivado Hardware Manager did not discover and display the JTAG chain and slowing the cable speed does not resolve the issue, see the following (assumes Digilent USB A-to-micro B cable is plugged into USB-to-JTAG configuration logic module U21 through J2): 

 





If following the above steps does not allow you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC.
Connect the Platform Cable USB to header J8, and connect to your PC.
Ensure Xilinx tools (preferably the latest version of tools that support the KCU116) are correctly installed.
Launch Vivado Hardware Manager - is the cable identified correctly?

 



If following the above steps does not allow you to initialize the JTAG chain, please review the Support Webpage for your available Support options.




5) JTAG Configuration


If the JTAG chain initializes, but JTAG configuration fails, check the following:

a) Verify the mode switch settings for JTAG configuration mode:

  • SW21-6 (M2) 1
  • SW21-5 (M1) 0
  • SW21-4 (M0) 1

 

b) In Vivado Hardware Manager, select a lower cable frequency and re-attempt configuration.

 

c) Pulse the PROG push button on the KCU116 (SW5).
Pulsing PROG will clear out any problems caused by power up ramp rate issues to the FPGA.

 

d) Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.
The Configuration Solution Center is available to address all questions related to Configuration.

 


If the above steps fail to enable JTAG configuration, please review the Support Webpage for your available Support options.

 


6) Master SPI configuration

The Vivado Hardware Manager can be used to indirectly program the QSPI flash devices (U2, U3) on the KCU116.

With SW21 set as follows:

  • SW21-6 (M2)  0
  • SW21-5 (M1)  0
  • SW21-4 (M0)  1

A bitstream programmed into the SPI flash devices is used to configure the UltraScale+ FPGA U1.  

If you have loaded a .mcs file into the SPI flash on the KCU116, and subsequent Master SPI configuration of the Kintex UltraScale+ device fails, the following points should be checked:

 

a) If the .mcs file is correctly loaded, you will see the selected FLASH device added to the JTAG chain.

By clicking on the flash device, you will see the MCS file successfully loaded.

If you do not see the FLASH device attached to the KU5P device, see the Vivado Design Suite User Guide: (UG908) Programming and Debugging.

b) Verify the mode switch settings for Master SPI configuration:

  • SW21-6 (M2)  0
  • SW21-5 (M1)  0
  • SW21-4 (M0)  1


c) In Vivado Hardware Manager, select a lower cable frequency and re-attempt configuration.

d) Pulse the PROG push button on the KCU116 (SW5), to attempt to reload the FPGA with the configuration image.

e) Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.  The Configuration Solution Center is available to address all questions related to Configuration.

If the above steps fail to enable SPI configuration, please review the Support Webpage for your available Support options.



 


7) PCIe

If the KCU116 configures correctly, but the PCIe interface does not operate as expected, check the following:

a) Do NOT plug a PC ATX power supply 6-pin connector into J52 on the KCU116 board. The ATX 6-pin connector has a different pinout than J52.
Connecting an ATX 6-pin connector into J52 will damage the KCU116 board and will void the board warranty.
To install and power the board correctly, follow the instructions given in (UG1239) KCU116 Evaluation Board User Guide.

b) Check J7, lane width, is set correctly for your application.

c) See one of the following Answer Records, covering Known Issues for PCI Express, including Kintex UltraScale+:


(Xilinx Answer 65751) UltraScale+ PCI Express Integrated Block - Release Notes and Known Issues Answer Record
(Xilinx Answer 68134) UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express - Integrated Debugging Features and Usage Guide

 

d) Review (Xilinx Answer 34536) - Xilinx Solution Center for PCI Express.

The Solution Center for PCI Express is available to address all questions related to the Xilinx solutions for PCI Express.

 

If the above steps fail to resolve the PCIe issue, please review the Support Webpage for your available Support options.

 



8) IBERT

Note: Running IBERT requires the installation of Vivado ILA.  

A device-locked license for this software is provided with the Kintex UltraScale+ KCU116 Evaluation Kit. The KCU116 can run IBERT testing for: FMC, PCIe, and zSFP.

If the KCU116 configures correctly, but IBERT does not operate as expected, check the following:

a) Ensure that all necessary hardware is connected to the KCU116 for IBERT testing.
More information can be found in XTP464 KCU116 Software Install and Board Setup and in XTP459 KCU116 GTY IBERT Design Creation, available on the KCU116 Documentation & Designs tab.

b) Download and run the KCU116 GTY IBERT Design, whichever version is appropriate for your silicon and software version.
It is recommended to always use the latest version of software which supports the KCU116, and associated version of the KCU116 GTY IBERT Example Design.
Follow the associated PDF. All are available from the KCU116 Documentation & Designs tab.

 


 

 

c) Read the KCU116 GTY IBERT Example Design document: KCU116 GTY IBERT PDF: XTP459.pdf and follow the instructions within.

d) IBERT Design Assistant: (Xilinx Answer 45562).

If the above steps fail to resolve the IBERT issue, please review the Support Webpage for your available Support options.

 


9) DDR4

If a problem is suspected with DDR4 / MIG, check the following:

a) Ensure that the DDR4 DIMM component memory is inserted correctly.

 


b) Download and run the KCU116 MIG Example Design, whichever version is appropriate for your silicon and software version.
It is recommended to always use the latest version of software which supports the KCU116, and associated version of the KCU116 MIG Example Design.
Follow the associated PDF. All are available from the KCU116 Documentation & Designs tab.

 

69315-12.jpg

 

 

c) Read the KCU116 MIG Example Design document: KCU116 MIG PDF: XTP461.pdf

d) Review (Xilinx Answer 34243) - Xilinx MIG Solution Center.
The Memory Interface Generator (MIG) Solution Center is available to address all questions related to MIG.

If the above steps fail to resolve the DDR4 issue, please review the Support Webpage for your available Support options.

 



10) Interface Tests

(Xilinx Answer 69859) - Kintex UltraScale+ FPGA KCU116 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the KCU116 are working correctly.

This Answer Record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.

If the above tests fail to resolve the issue, please review the Support Webpage for your available Support options.

 



11) Known Issues for KCU116

All Known Issues for the Kintex UltraScale+ FPGA KCU116 Evaluation Kit are listed in (Xilinx Answer 68360) - Kintex UltraScale+ FPGA KCU116 Evaluation Kit - Known Issues and Release Notes Master Answer Record.

If the issue you are faced with is not listed in the Known Issues and Release Notes Master Answer Record, and the steps above fail to resolve the issue, please review the Support Webpage for your available Support options.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43748 Xilinx Boards and Kits - Debug Assistant N/A N/A
AR# 69315
Date 11/13/2017
Status Active
Type General Article
Boards & Kits
  • Kintex UltraScale Plus FPGA KCU116 Evaluation Kit
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