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AR# 69443

2017.1 Vivado IP Flows - Abnormal Program Termination for Kintex UltraScale design when running OOC Synthesis on AXI PCIE3 IP core


In my Kintex UltraScale design, when I run out of context (OOC) synthesis on an AXI PCIE3 IP instance, I see the following message:

Abnormal program termination (11)

In the runme.log file, the error message is seen soon after the Finished RTL Optimization Phase 2 stage.


This abnormal program termination has been seen with Vivado 2017.1 when all of the following conditions are true:

  • Running on a Centos 7 64-bit operating system
  • Using a Kintex UltraScale device
  • AXI PCIE3 IP instance
  • Using OOC Synthesis

This issue has been fixed in Vivado 2017.2.

To prevent the abnormal program termination in Vivado 2017.1, set the following parameter in the Tcl console before generating the output products for the IP core:

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter xilinxGLogicGenerator false
AR# 69443
Date 11/30/2017
Status Active
Type Known Issues
  • Kintex UltraScale
  • Vivado Design Suite - 2017.1
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