In my Kintex UltraScale design, when I run out of context (OOC) synthesis on an AXI PCIE3 IP instance, I see the following message:
In the runme.log file, the error message is seen soon after the Finished RTL Optimization Phase 2 stage.
This abnormal program termination has been seen with Vivado 2017.1 when all of the following conditions are true:
This issue has been fixed in Vivado 2017.2.
To prevent the abnormal program termination in Vivado 2017.1, set the following parameter in the Tcl console before generating the output products for the IP core:
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter xilinxGLogicGenerator false