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AR# 69477

UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2017.1/2017.2) - Timed (unsafe) between source clock sys_clk and destination clock pipe_clk

Description

Version Found: v4.3 / v4.3 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 57945)

When implementing the default UltraScale FPGA Gen3 Integrated Block for PCI Express example design, the clock interaction report shows Timed (unsafe) between sys_clk (Source Clock) and pipe_clk (Destination Clock).


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

This is a known issue to be fixed in a future release of the core.

To fix the issue in Vivado 2017.1/Vivado 2017.2, please install the patch attached to this Answer Record as described in the 'patch_readme' directory of the patches attached.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

07/18/2017 - Initial release

Attachments

Associated Attachments

AR# 69477
Date 07/25/2017
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2017.1
  • Vivado Design Suite - 2017.2
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)
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