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AR# 69903

2017.3 Vivado IP Release Notes - All IP Change Log Information Article

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2017.3 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2017 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

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100M/1G TSN Subsystem (1.0)

* Version 1.0

* First Public Release of IP

10G Ethernet MAC (15.1)

* Version 15.1 (Rev. 4)

* General: Added note to GUI suggesting usage of 10G/25G Ethernet Subsystem for UltraScale and UltraScale+ designs

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 10)

* General: Added note to GUI suggesting usage of 10G/25G Ethernet Subsystem for UltraScale and UltraScale+ designs

* Revision change in one or more subcores

10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 6)

* General: Added note to GUI suggesting usage of 10G/25G Ethernet Subsystem for UltraScale and UltraScale+ designs

* Revision change in one or more subcores

10G/25G Ethernet Subsystem (2.3)

* Version 2.3

* Feature Enhancement: Updated for CR

* Feature Enhancement: Updated RSFEC and runtime switch dependency

* Feature Enhancement: Added RUNTIME SWITCHING support for UltraScale Plus -1 and -1L speed grades

* Feature Enhancement: Updated for IP Integrator board assistance support for vcu118 board

* Feature Enhancement: TXOUTCLKSEL and RXOUTCLKSEL input ports should be driven with 3'b101

* Feature Enhancement: Removed tx_ptp_rxtstamp_in for ptp 1 step configuration

* Revision change in one or more subcores

1G/10G/25G Switching Ethernet Subsystem (1.0)

* Version 1.0

* Initial release of 1/10 Ethernet switching subsystem with GTHE4 support.

1G/2.5G Ethernet PCS/PMA or SGMII (16.1)

* Version 16.1 (Rev. 1)

* Unwanted constraint of create_clock on rxoutclk removed from XDC

* Incorrect dumping of transceiver file in example design folder corrected when GT in example design is chosen.

* Revision change in one or more subcores

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 8)

* No changes

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 14)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 12)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 14)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 12)

* Revision change in one or more subcores

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

40G/50G Ethernet Subsystem (2.3)

* Version 2.3

* Feature Enhancement: CR

* Feature Enhancement: Updated for IP Integrator board assistance support for vcu118 board

* Other: added support to send continuous packets

* Unknown category port_changes: Added TXOUTCLKSEL and RSOUTCLKSEL ports for default configuration

* Unknown category port_changes: Removed tx_ptp_rxtstamp_in for ptp 1 step configuration

* Revision change in one or more subcores

64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 8)

* No changes

7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 7)

* No changes

7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 6)

* Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph

* Feature Enhancement: Enabled support for cpg238 package for devices - xc7a12t,xc7a12ti,xc7a12tl,xc7a25t,xc7z25ti and xc7a25tl

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 12)

* General: Updates to example design. No Functional changes

* Revision change in one or more subcores

AMM AXI Bridge (1.0)

* Version 1.0

* Initial Vivado Release

AXI 1G/2.5G Ethernet Subsystem (7.1)

* Version 7.1 (Rev. 1)

* General: Refer to tri_mode_ethernet_mac v9.0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core.

* General: axi_ethernet_buffer enabled in case of SGMII with 1588

* Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 12)

* General: Updates to example design. No functional changes.

* Revision change in one or more subcores

AXI AMM Bridge (1.0)

* Version 1.0 (Rev. 4)

* General: Updated to example design. No functional changes

* Revision change in one or more subcores

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 12)

* General: Updates to example design. No functional changes.

* Revision change in one or more subcores

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 12)

* General: Migrated to use XPM Memory in place of Block Memory Generator

AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0 (Rev. 4)

* Bug Fix: Fixed issue with the generation of example design in IP Integrator canvas.

* Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph

* Bug Fix: Update internal RTL module naming to allow multiple PCIe IP to be instantiated in a design

* Feature Enhancement: Added Byte Enable to the Snooping Logic hanging of the CFG_MGMT_* interface (Block Bridge access) to allow per-Byte only access

* Feature Enhancement: Enabled Prefetch Mem Base/Limit 32/64-bit register and Memory Base/Limit register for Root Port configuration

* Revision change in one or more subcores

AXI CAN (5.0)

* Version 5.0 (Rev. 17)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 14)

* General: Updates to example design

* General: IP RTL updated to use XPM FIFO. No functional changes

* Revision change in one or more subcores

AXI Chip2Chip Bridge (5.0)

* Version 5.0

* Feature Enhancement: IP now comes with a AXI4 safety circuit

* Feature Enhancement: IP version updated as there is a change in IO / Lane calculations

* Revision change in one or more subcores

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 13)

* Update subcore IP FIFO Generator to v13.2; reduce IP clocking XDC due to pathways handled by fifo-gen.

* Revision change in one or more subcores

AXI Crossbar (2.1)

* Version 2.1 (Rev. 15)

* Revision change in one or more subcores

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 13)

* Update subcore IP FIFO Generator to v13.2.

* Revision change in one or more subcores

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 14)

* Update subcore IP FIFO Generator to v13.2; reduce IP clocking XDC due to pathways handled by fifo-gen.

* Revision change in one or more subcores

AXI DataMover (5.1)

* Version 5.1 (Rev. 16)

* General: DRE now supported for width up to 512

* General: IP RTL updated to use XPM FIFO

* Revision change in one or more subcores

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 15)

* General: AXI Lite clock domain has been made independent

* General: IP RTL modified to use XPM FIFO

* General: Updates to example design

* Revision change in one or more subcores

AXI EMC (3.0)

* Version 3.0 (Rev. 14)

* General: Updates to example design. No functional changes

* Revision change in one or more subcores

AXI EPC (2.0)

* Version 2.0 (Rev. 17)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 16)

* Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 12)

* General: IP updated to use FIFO Generator v13.2

* General: Updates to XDC. No functional changes

* Revision change in one or more subcores

AXI GPIO (2.0)

* Version 2.0 (Rev. 16)

* General: Updated the IP to report default value of registers

* Revision change in one or more subcores

AXI HWICAP (3.0)

* Version 3.0 (Rev. 18)

* General: XDC file updated. No Functional changes

* Revision change in one or more subcores

AXI IIC (2.0)

* Version 2.0 (Rev. 17)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Interconnect (2.1)

* Version 2.1 (Rev. 15)

* Bug Fix: Updated SYNCHRONIZATION_STAGES default value from 2 to 3.

* Revision change in one or more subcores

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 10)

* No changes

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 12)

* Revision change in one or more subcores

AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Memory Mapped To PCI Express (2.8)

* Version 2.8 (Rev. 6)

* Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 13)

* Revision change in one or more subcores

AXI Multi Channel Direct Memory Access (1.0)

* Version 1.0

* General: New IP

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 16)

* Feature Enhancement: ID width up to 32 now supported for AXI4 Slots

* Other: FIFO Generator instances replaced with XPM FIFO

* Revision change in one or more subcores

AXI Protocol Checker (2.0)

* Version 2.0

* General: Removed user parameter only ENABLE_EXT_CHECKS and Fixed the pc_status width to 160

* Revision change in one or more subcores

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 14)

* Revision change in one or more subcores

AXI Protocol Firewall (1.0)

* Version 1.0 (Rev. 2)

* General: Customization GUI improvements

* Revision change in one or more subcores

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 13)

* General: Example design updated to use XPM memory.

* Revision change in one or more subcores

AXI Register Slice (2.1)

* Version 2.1 (Rev. 14)

* Bug Fix: Fixed bug where changing the value of the PROTOCOL parameter would cause the loss of any assignment of value 9 to the REG_* parameters.

* New Feature: Added SLR-crossing mode, including TDM at half-width at 2x CLK.

* Revision change in one or more subcores

AXI SmartConnect (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: Changed default number of synchronization stages used in asynchronous clock conversion from 2 to 3 to improve MTBF characteristics

* Bug Fix: Fixed customization GUI issue that occasionally caused an error message to appear in the log describing undefined meta-parameter SC_CONFIG_ALL

* Feature Enhancement: Improved resource utilization when SmartConnect when all devices are AXI4-Lite, are synchronous to the same clock and have the same data width.

* Revision change in one or more subcores

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 18)

* General: IP updated to use FIFO Generator v13.2

* General: IP XDC updated. No Functional changes

* Revision change in one or more subcores

AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 6)

* Feature Enhancement: Timer interval is now made programmable

* Revision change in one or more subcores

AXI Timer (2.0)

* Version 2.0 (Rev. 16)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Traffic Generator (3.0)

* Version 3.0

* General: M_AXI interface updated to be Read Only, Write Only or Read_Write

* General: IP RTL updated to use xpm_memory

* Revision change in one or more subcores

AXI UART16550 (2.0)

* Version 2.0 (Rev. 16)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 15)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Uartlite (2.0)

* Version 2.0 (Rev. 18)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

AXI Verification IP (1.1)

* Version 1.1

* versionless of package, interface and PC

* Revision change in one or more subcores

AXI Video Direct Memory Access (6.3)

* Version 6.3 (Rev. 2)

* Feature Enhancement: Vertical Flip feature added for Write Path

* Other: AXI4Lite clock domain separated from others clock domains

* Other: Example design updated to use XPM memory

* Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 16)

* General: Asynchronous reset flops moved to use synchronous reset

* Revision change in one or more subcores

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 11)

* Feature Enhancement: Asynchronous reset flops are moved to use synchronous reset

* Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 12)

* General: CLK_SRC property removed for the clocks from the XDC constraints. No functional changes

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 14)

* Revision change in one or more subcores

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 15)

* Updated XDC in sync with FIFO changes

* Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 13)

* Revision change in one or more subcores

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 15)

* Updated to use FIFO Generator v13.2

* Updated XDC ttcl in sync with FIFO changes

* Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 13)

* Initializing Valid/Ready Outputs to zero before reset kicks in

* Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 15)

* Revision change in one or more subcores

AXI4-Stream Protocol Checker (1.2)

* Version 1.2

* Added Reset Pulse Assertion Check

* Revision change in one or more subcores

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 14)

* New Feature: Expose REG_CONFIG parameter in Config GUI to support user selection of register-slice type (default remains unchanged).

* New Feature: Added SLR-crossing modes, including TDM at half-width at 2x CLK

* New Feature: Added Bypass-Endpoint mode to allow interface properties to be treated as fixed values during IP Integrator design validation.

* Revision change in one or more subcores

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 14)

* Revision change in one or more subcores

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 14)

* Allow Tvalid low cycles to be 0 for Tlast arbitration

* Revision change in one or more subcores

AXI4-Stream Verification IP (1.1)

* Version 1.1

* versionless of package, interface and PC

* Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 7)

* General: Updated core to utilize XPM_FIFO

* Revision change in one or more subcores

Accumulator (12.0)

* Version 12.0 (Rev. 11)

* Revision change in one or more subcores

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 11)

* Revision change in one or more subcores

Aurora 64B66B (11.2)

* Version 11.2 (Rev. 2)

* General: FIFO Generator version upgrade.

* General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides

* Revision change in one or more subcores

Aurora 8B10B (11.1)

* Version 11.1 (Rev. 2)

* General: GTP attribute update in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices

* General: Standard CC logic is enabled after lane-up itself instead of waiting till channel-up condition

* General: Added optional parameter C_DOUBLE_GTRXRESET to assert additional reset for handling errors during lane initialization in duplex links with very high PPM differences

* General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides

* Revision change in one or more subcores

Binary Counter (12.0)

* Version 12.0 (Rev. 11)

* Revision change in one or more subcores

Block Memory Generator (8.4)

* Version 8.4

* General: Safety Circuit option is enabled by default if reset option in any one port is enabled

CANFD (1.0)

* Version 1.0 (Rev. 7)

* General: Updated example design subcore version, no functional changes

* Revision change in one or more subcores

CIC Compiler (4.0)

* Version 4.0 (Rev. 12)

* Revision change in one or more subcores

CORDIC (6.0)

* Version 6.0 (Rev. 12)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

CPRI (8.8)

* Version 8.8

* Port Change: Added optional output port mmcm_locked_out for 7 Series parts.

* Port Change: Enabled optional output port txusrclk_out for 8b10b line rates on 24.3G capable cores.

* Port Change: Removed deprecated ports gt_reset_req and gt_reset_req_out for 7 Series devices.

* Feature Enhancement: Added support for Hard FEC on receive data path for UltraScale+ parts with 100G RS-FEC support.

* Feature Enhancement: Added Freerun clock rate field to the GUI. Used by the UltraScale GT wizard reset block.

* Other: Replaced fifo_generator subcore with XPM_FIFO.

* Revision change in one or more subcores

Chroma Resampler (4.0)

* Version 4.0 (Rev. 12)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Clocking Wizard (5.4)

* Version 5.4 (Rev. 2)

* General: Internal GUI changes. No effect on the customer design. Added support for Spartan 7 devices

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 12)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Compact GT (1.0)

* Version 1.0

* Initial release

Complex Multiplier (6.0)

* Version 6.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Concat (2.1)

* Version 2.1 (Rev. 1)

* No changes

Constant (1.1)

* Version 1.1 (Rev. 3)

* No changes

Convolution Encoder (9.0)

* Version 9.0 (Rev. 12)

* General: Updated comments in VHDL files

* Revision change in one or more subcores

DDR3 SDRAM (MIG) (1.4)

* Version 1.4 (Rev. 2)

* Bug Fix: (Xilinx Answer 69827) UltraScale+ Memory IP - The SFVB784 package has incorrect data rates in PL Memory Interfaces

* Revision change in one or more subcores

DDR4 SDRAM (MIG) (2.2)

* Version 2.2 (Rev. 2)

* Bug Fix: (Xilinx Answer 69827) UltraScale+ Memory IP - The SFVB784 package has incorrect data rates in PL Memory Interfaces

* Feature Enhancement: Clamshell support for DDR4 ping-pong PHY mode

* Revision change in one or more subcores

DDS Compiler (6.0)

* Version 6.0 (Rev. 14)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

DMA/Bridge Subsystem for PCI Express (PCIe) (4.0)

* Version 4.0

* Bug Fix: Fixed issue with the generation of example design in IP Integrator canvas

* Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph

* Bug Fix: Added missing ports for 'Include GT Wizard in Example Design' mode

* Bug Fix: Corrected GT DRP address width for UltraScale Plus device family

* Bug Fix: Fixed connection between cfg_err_cor_in or cfg_err_uncor_in signals and XDMA Bridge internal register. Remove unused cfg_err_uncor_in port in multi PF designs

* Bug Fix: Removed invalid dependency on M_AXIB_Wvalid and M_AXIB_AWready signal

* Bug Fix: Fixed Address Translation mechanism in RP AXI Bridge mode when no BAR is enabled

* Bug Fix: Fixed Address Translation for 64-bit AXI/PCIe BAR

* Feature Enhancement: Added option to enable external BUFG_GT/SYNC for sys_clk

* Feature Enhancement: Moved phy_clk module in support wrapper when Include GT Wizard in Example Design mode is selected

* Feature Enhancement: Added GT COMMON sharing support

* Feature Enhancement: Added Tandem support for VU7P, KU15P, ZU19 devices

* Feature Enhancement: Added support for xcvu33p, xazu4ev and xazu5ev devices

* Feature Enhancement: Enabled x8g3 configuration support for -1 and -2LV speedgrades for all the devices and packages

* Other: Removed s_axib_wuser and s_axib_ruser signal in AXI Bridge mode

* Revision change in one or more subcores

DSP48 Macro (3.0)

* Version 3.0 (Rev. 15)

* Revision change in one or more subcores

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 12)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Debug Bridge (3.0)

* Version 3.0

* Added new device support for Virtex UltraScale+ HBM devices

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 14)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

DisplayPort (7.0)

* Version 7.0 (Rev. 6)

* Bug Fix: PRBS7 alignment at IP level to support PHY checks

* Bug Fix: 4K DCI RB2 timing support

* Revision change in one or more subcores

DisplayPort RX Subsystem (2.1)

* Version 2.1

* Feature Enhancement: Design Example Support

* Revision change in one or more subcores

DisplayPort TX Subsystem (2.1)

* Version 2.1

* Bug Fix: PRBS7 alignment at IP level to support PHY checks

* Bug Fix: 4K DCI RB2 timing support

* Feature Enhancement: Design Example Support

* Revision change in one or more subcores

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 12)

* General: Internal device family change, no functional changes

Divider Generator (5.1)

* Version 5.1 (Rev. 12)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Double Data Rate Sampling (1.0)

* Version 1.0

* No changes

ECC (2.0)

* Version 2.0 (Rev. 12)

* No changes

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 16)

* General: Updated example design subcore version. No Functional changes

* Revision change in one or more subcores

FEC 5G Common Utilities (1.0)

* Version 1.0

* Initial release

FIFO Generator (13.2)

* Version 13.2

* Feature Enhancement: Enable Safety Circuit option is made default for BRAM based FIFOs when Asynchronous Reset is selected

* Feature Enhancement: All outputs are made synchronous to respective clock domain when Enable Safety Circuit option is selected

* Feature Enhancement: All outputs are invalid for reset duration + 60 slowest clock cycles when Enable Safety Circuit option is selected

* Feature Enhancement: All outputs are invalid for reset duration + 30 slowest clock cycles when Enable Safety Circuit option is not selected

* Feature Enhancement: The outputs of FIFO Generator may be Xs for initial few clock cycles if the core is configured without reset. 

It is recommended to wait for 15 slowest clock cycles at the beginning of behavioral simulation (from time 0) before accessing the FIFO

FIR Compiler (7.2)

* Version 7.2 (Rev. 9)

* Feature Enhancement: Increase the maximum number of parallel inputs from 64 to 256

* Revision change in one or more subcores

Fast Fourier Transform (9.0)

* Version 9.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Fibre Channel 32GFC RS-FEC (1.0)

* Version 1.0 (Rev. 4)

* General: Added support for Virtex HBM UltraScale+ devices.

* Revision change in one or more subcores

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 8)

* No changes

FlexO 100G RS-FEC (1.0)

* Version 1.0 (Rev. 4)

* General: Added support for Virtex HBM UltraScale+ devices.

* Revision change in one or more subcores

Floating-point (7.1)

* Version 7.1 (Rev. 5)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

G.709 FEC Encoder/Decoder (2.3)

* Version 2.3 (Rev. 1)

* Revision change in one or more subcores

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 14)

* Revision change in one or more subcores

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 15)

* Revision change in one or more subcores

Gamma Correction (7.0)

* Version 7.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Gamma LUT (1.0)

* Version 1.0

* First version released

* Programmable gamma table supports gamma correction or any user defined function

* Three channel independent look-up tables

* One, two, four or eight pixel-wide AXI4-Stream video interface

* Video resolution support up to UHD at 60 fps

* 8 and 10 bits per component support

Gmii to Rgmii (4.0)

* Version 4.0 (Rev. 4)

* No changes

HDCP (1.0)

* Version 1.0 (Rev. 3)

* Bug Fix: Fixed problem where interrupt mask setting was not causing interrupt line to de-assert

HDCP 2.2 Cipher (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Fixed IRQ interface type warning

HDCP 2.2 Montgomery Modular Multiplier (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes

HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: Override crossbar protocol mode to AXI4-Lite

HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: Override crossbar protocol mode to AXI4-Lite

HDMI 1.4/2.0 Receiver (3.0)

* Version 1.1

* No changes

HDMI 1.4/2.0 Receiver Subsystem (3.0)

* Version 3.0

* Bug Fix: Synchronized AXI master reset for all processor blocks

* Bug Fix: Updated ACR controller to support HDMI 2.0

* Bug Fix: Updated to block reading VTC register when no video clock is present

* Bug Fix: Updated Example Design C_HDMI_FAST_SWITCH to have default as true

* Bug Fix: Fixed intermittent RX Stream lock issue for HDMI 2.0 Line Rate

* Bug Fix: Fixed issue with swapped horizontal front porch and back porch

* Bug Fix: Fixed issue with color shift

* Bug Fix: HDCP 2.2 RxStatus Fix

* Bug Fix: Updated axis reset to be fully synchronous

* Bug Fix: Updated axis clock to 150Mhz for 4PPC for better timing closure

* Feature Enhancement: Example design supporting core upversion (vid_phy_controller from v2.0 to v2.1)

* Feature Enhancement: Example design topology supports (TX-Only, RX-Only, Pass-through)

* Feature Enhancement: Example design VPHY Configuration Support (NI-DRU Enable/Disable, TXPLL selection, RXPLL selection)

* Feature Enhancement: Example design new board supports (ZCU102, ZCU106)

* Feature Enhancement: Example design subcore addressing mechanism changed from auto-assign to fix address

HDMI 1.4/2.0 Transmitter (3.0)

* Version 2.0

* No changes

HDMI 1.4/2.0 Transmitter Subsystem (3.0)

* Version 3.0

* Bug Fix: Synchronized AXI master reset for all processor blocks

* Bug Fix: Updated ACR controller to support HDMI 2.0

* Bug Fix: Updated to block reading VTC register when no video clock is present

* Bug Fix: Updated Example Design C_HDMI_FAST_SWITCH to have default as true

* Bug Fix: Implemented synchronous axis reset to fix Vivado DRC warnings

* Bug Fix: Updated axis reset to be fully synchronous

* Bug Fix: Added YUV420 and YUV444 support to video mask

* Bug Fix: Updated DDC peripheral to support longer clock stretching

* Bug Fix: Updated axis clock to 150Mhz for 4PPC for better timing closure

* Feature Enhancement: Example design supporting core upversion (vid_phy_controller from v2.0 to v2.1)

* Feature Enhancement: Example design topology supports (TX-Only, RX-Only, Pass-through)

* Feature Enhancement: Example design VPHY Configuration Support (NI-DRU Enable/Disable, TXPLL selection, RXPLL selection)

* Feature Enhancement: Example design new board supports (ZCU102, ZCU106)

* Feature Enhancement: Example design subcore addressing mechanism changed from auto-assign to fix address

High Speed SelectIO Wizard (3.2)

* Version 3.2 (Rev. 2)

* Bug Fix: Updated the range of M and D of PLL for UltraScale+ devices

* New Feature: Added option to allow the RXBITSLICE output to user before bitslip begins

* New Feature: Added feature to give the recommended set of PLL input frequencies

* Other: Added warning in GUI to discourage customers from using Edge Aligned RX designs with non-0 delay_values

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 16)

* No changes

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 16)

* Updated device specific constraints.

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 16)

* No changes

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 13)

* Updated the XDC to loc the BUFG used for cfgclk

IBERT UltraScale GTH (1.3)

* Version 1.3 (Rev. 8)

* Updated supported device list.

* Revision change in one or more subcores

IBERT UltraScale GTY (1.2)

* Version 1.2 (Rev. 8)

* Added device support for new Virtex and Zynq device family.

* Revision change in one or more subcores

IEEE 802.3 200G RS-FEC (1.0)

* Version 1.0

* General: First version of core

IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 6)

* General: Added support for Virtex HBM UltraScale+ devices.

* Revision change in one or more subcores

IEEE 802.3 400G RS-FEC (1.0)

* Version 1.0

* First version of core

IEEE 802.3 50G RS-FEC (1.0)

* Version 1.0 (Rev. 6)

* General: Added support for Virtex HBM UltraScale+ devices.

* Revision change in one or more subcores

IEEE 802.3bj 100G RS-FEC (1.0)

* Version 1.0 (Rev. 10)

* General: Added support for Virtex HBM UltraScale+ devices.

* General: Modified sampling of TX FEC bypass control at reset: now correctly sampled even if Rx clock is not running.

* General: Added alignment marker monitoring as per IEEE 802.3 revision request 1299.

* Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2 (Rev. 4)

* Added new Virtex UltraScale+ HBM device support

IOModule (3.1)

* Version 3.1 (Rev. 2)

* General: Use instantiated primitive for synchronization, no functional changes

Image Enhancement (8.0)

* Version 8.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

In System IBERT (1.0)

* Version 1.0 (Rev. 4)

* Updated synchronization logic for RXRATE port.

* Revision change in one or more subcores

Interlaken 150G (2.3)

* Version 2.3

* Feature Enhancement: CR

* Feature Enhancement: Updated for IP Integrator board assistance support for vcu118 board

* Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 11)

* Revision change in one or more subcores

JESD204 (7.2)

* Version 7.2

* Bug Fix: Fixed issue causing RXLPMEN values to be incorrect when shared logic in the core is used, see (Xilinx Answer 69507)

* Bug Fix: Fixed issue where TX PRBSSEL bits would be incorrectly set to enable D21.5 when PRBS15 was selected

* Feature Enhancement: Core will now resync automatically to a misaligned SYSREF when SYSREF ALWAYS = 1

* Revision change in one or more subcores

JESD204 PHY (4.0)

* Version 4.0

* Bug Fix: Fixed issue causing RXLPMEN values to be incorrect when neither AXI-Lite nor Transceiver Debug are enabled. See (Xilinx Answer 69508)

* Bug Fix: Fixed issue causing CPLL_PD values incorrect if CPLL is not used and AXI-Lite is not enabled. See (Xilinx Answer 69510)

* Feature Enhancement: Added option to choose between JESD204B and JESD204C IP core interfaces, this replaces 32/64-bit option.

* Feature Enhancement: Added 8B10B signaling ports to JESD204C IP core

* Revision change in one or more subcores

JESD204C (2.0)

* Version 2.0

* Feature Enhancement: Added FEC encoder and decoder

* Feature Enhancement: Added 8b10b signaling ports to the PHY interface

* Other: Updated metabit bit positions for CRC and CMD modes as per standard change

* Revision change in one or more subcores

JTAG to AXI Master (1.2)

* Version 1.2 (Rev. 4)

* Updated FIFO Generator version

* Revision change in one or more subcores

LDPC Encoder/Decoder (1.0)

* Version 1.0

* General: Initial release

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 13)

* Feature Enhancement: Added support for XPM memory

* Other: Added support for XA Zynq UltraScale+ and XA Spartan-7 devices

LPDDR3 SDRAM (MIG) (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: (Xilinx Answer 69827) UltraScale+ Memory IP - The SFVB784 package has incorrect data rates in PL Memory Interfaces

* Revision change in one or more subcores

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 14)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 12)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

LTE RACH Detector (3.1)

* Version 3.1

* General: Added Optional clken pin, to provide clock enable

* General: Added optional axiclk pin. When enabled, provides separate clock domain for AXI register interface.

* General: Added optional axiclken pin. provides optional clock enable to axiclk domain.

* Revision change in one or more subcores

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 13)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 9)

* No changes

MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 6)

* No changes

MIPI CSI-2 Rx Subsystem (3.0)

* Version 3.0

* Port Change: Grouped *rxp, *rxn ports as *mipi_phy_if interface

* New Feature: Added example design

* New Feature: Added board support for FMC LI-IMX274MIPI-FMC V1.0 on ZCU102 HPC0

* Revision change in one or more subcores

MIPI CSI-2 Tx Controller (1.0)

* Version 1.0 (Rev. 2)

* No changes

MIPI CSI-2 Tx Subsystem (2.0)

* Version 2.0

* Port Change: Grouped *txp, *txn ports as *mipi_phy_if interface

* Bug Fix: MIPI CSI-2 Tx Controller - controller ready behavior now considers MIPI D-PHY Initialization Completion

* Revision change in one or more subcores

MIPI D-PHY (4.0)

* Version 4.0

* Port Change: Added cl_tst_clk_out, dl_tst_clk_out, cl_tst_clk_in and dl_tst_clk_in ports for 7 Series D-PHY TX IP configuration

* Port Change: Grouped *txp,*txn, *rxp, *rxn ports as *mipi_phy_if interface

* Bug Fix: Fixed ulpsactivenot deassertion for D-PHY RX IP configuration

* Bug Fix: Added BUFIO in 7-Series TX configuration

* Bug Fix: Removed tangling mmcm_lock_out port in D-PHY RX configuration

* Bug Fix: Updated IODELAY group name to change dynamically for 7 Series D-PHY RX IP configuration

* Bug Fix: Updated FIFO_WRCLK_OUT constraint for UltraScale+ D-PHY RX configuration

* Bug Fix: Fixed High-Speed mode to Low-Power mode switching overshoot issue in 7 Series D-PHY TX IP with OBUFTDS configuration

* New Feature: Added board support for FMC LI-IMX274MIPI-FMC V1.0 on ZCU102 HPC0

* Revision change in one or more subcores

MIPI DSI Tx Controller (1.0)

* Version 1.0 (Rev. 4)

* No changes

MIPI DSI Tx Subsystem (2.0)

* Version 2.0

* Port Change: Grouped *txp, *txn ports as *mipi_phy_if interface

* New Feature: Added board support for FMC LI-IMX274MIPI-FMC V1.0 on ZCU102 HPC0

* Revision change in one or more subcores

Mailbox (2.1)

* Version 2.1 (Rev. 8)

* Feature Enhancement: Added FIFO reset functionality

* Other: Use synchronous reset for asynchronous FIFO

Memory Helper Core (1.4)

* Version 1.4

* No changes

Memory Interface Generator (MIG 7 Series) (4.0)

* Version 4.0 (Rev. 5)

* General: Vivado 2017.3 software support.

* General: Added support for CPG236 packaged FPGA

MicroBlaze (10.0)

* Version 10.0 (Rev. 4)

* Bug Fix: Corrected victim cache address size computation causing synthesis error. Versions that have this issue: 10.0. Can only occur with performance optimization when using instruction victim cache with extended address and MMU virtual mode enabled.

* Bug Fix: Ensure that a write is not attempted when the outstanding number of writes on M_AXI_DC has reached the maximum value 31. Can only occur with data cache enabled when writing to the cacheable address range.

* Feature Enhancement: Include preset configurations for microcontroller, real-time, and application

* Feature Enhancement: Add extended debug event trace

* Feature Enhancement: Add support for XPM memory

* Other: Added support for XA Zynq UltraScale+ and XA Spartan-7 devices

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 11)

* Feature Enhancement: Added option to set parallel debug interface to AXI

* Feature Enhancement: Support Xilinx Virtual Cable (XVC) debug connection

MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 6)

* Feature Enhancement: Added support for XPM memory

* Revision change in one or more subcores

Multiplier (12.0)

* Version 12.0 (Rev. 13)

* Revision change in one or more subcores

Multiply Adder (3.0)

* Version 3.0 (Rev. 11)

* Revision change in one or more subcores

Mutex (2.1)

* Version 2.1 (Rev. 8)

* No changes

PCIe PHY IP (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: Update in pipe_clk constraint for UltraScale devices

* Feature Enhancement: Added xcvu9p device support

* Feature Enhancement: For UltraScale family GT Wizard Sub IP version updated from v1_5 to v1_7

* Feature Enhancement: An option added to enable GT DRP ports for UltraScale+ devices

* Revision change in one or more subcores

Partial Reconfiguration Controller (1.2)

* Version 1.2

* Bug Fix: Fixed a corner case where the VSM could stay in SHUTDOWN if the RESTART command came on the clock cycle after reset was released.

* Bug Fix: Fixed a rare corner case where a PROCEED command (issued using AXIS) for SW Shutdown could be missed if it occurred within one clock of a PROCEED command (issued using AXI-LITE) for SW Startup.

* New Feature: Added support bitstream compression

* Other: Changed from using the fifo_generator to xpm_fifo

* Revision change in one or more subcores

Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 5)

* General: Modified OOC XDC file to remove the HD.CLK_SRC properties which are no longer needed

Peak Cancellation Crest Factor Reduction (6.1)

* Version 6.1 (Rev. 2)

* Revision change in one or more subcores

Processor System Reset (5.0)

* Version 5.0 (Rev. 12)

* General: Reset outputs initialized with a POR value

QDRII+ SRAM (MIG) (1.4)

* Version 1.4 (Rev. 2)

* Updated for 2017.3

* Revision change in one or more subcores

QDRIV SRAM (MIG) (2.0)

* Version 2.0 (Rev. 2)

* Updated for 2017.3

* Revision change in one or more subcores

QDRIV SRAM PHY IP (2.0)

* Version 1.2

* No changes

QSGMII (3.4)

* Version 3.4 (Rev. 1)

* Bug Fix: Mapping for Resetdone changed from CPLLLOCK to combination of resetdone_tx and resetdone_rx for GTXE2 devices

* Revision change in one or more subcores

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 11)

* Revision change in one or more subcores

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 11)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

RLDRAM3 (MIG) (1.4)

* Version 1.4 (Rev. 2)

* Bug Fix: (Xilinx Answer 69827) UltraScale+ Memory IP - The SFVB784 package has incorrect data rates in PL Memory Interfaces

* Feature Enhancement: Updated calibration code for Cisco

* Revision change in one or more subcores

RXAUI (4.4)

* Version 4.4 (Rev. 1)

* General: GTP Wizard settings update for RXLPM_BIAS_STARTUP_DISABLE for specific Artix devices

* Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 13)

* Revision change in one or more subcores

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 12)

* Bug Fix: This revision fixes an issue that could occur when the core has an S_AXIS_CTRL channel input. 

If a single control value was written before any data was written then s_axis_input_tready would not remain high for the entire codeword to be input: (Xilinx Answer 69370)

* Revision change in one or more subcores

S/PDIF (2.0)

* Version 2.0 (Rev. 17)

* General: IP updated to use FIFO Generator v13.2

* General: Updates to IP XDC. No Functional changes

* Revision change in one or more subcores

SC EXIT (1.0)

* Version 1.0 (Rev. 5)

* Feature Enhancement: When writing from a wide master to an AXI4-Lite slave, suppress writing any words in which WSTRB is all-zeroes.

* Feature Enhancement: Added Single Issuing Mode for Low Area solution.

* Feature Enhancement: Extend range of M_MAX_BURST_LENGTH: if 0, force Splitter into bypass for low-area QOR.

SC MMU (1.0)

* Version 1.0 (Rev. 5)

* Feature Enhancement: Added Single Issuing Mode for Low Area solution

SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 5)

* Feature Enhancement: Added Single Issuing Mode for Low Area solution

SC SPLITTER (1.0)

* Version 1.0 (Rev. 2)

* No changes

SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 6)

* Feature Enhancement: Added Single Issuing Mode for Low Area solution

SDI RX to Video Bridge (2.0)

* Version 2.0

* Use as hidden subcore in UHDSDI RX subsystem

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 8)

* No changes

SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 5)

* General: Added UltraScale Plus family support

SMPTE UHD-SDI RX (1.0)

* Version 1.0

* Initial release

SMPTE UHD-SDI RX SUBSYSTEM (1.0)

* Version 1.0

* New Feature: Added pass through example design based on ZCU106 board

* New Feature: Supports SMPTE ST 259: SD-SDI at 270 Mb/s

* New Feature: Supports SMPTE RP 165: EDH for SD-SDI

* New Feature: Supports SMPTE ST 292: HD-SDI at 1.485 Gb/s and 1.485/1.001 Gb/s

* New Feature: Supports SMPTE ST 372: Dual Link HD-SDI

* New Feature: Supports SMPTE ST 424: 3G-SDI with data mapped by any ST 425-x mapping at 2.97 Gb/s and 2.97/1.001 Gb/s

* New Feature: Supports SMPTE ST 2081-1: 6G-SDI with data mapped by any ST 2081-x mapping at 5.94 Gb/s and 5.94/1.001 Gb/s

* New Feature: Supports SMPTE ST 2082-1: 12G-SDI with data mapped by any ST 2082-x mapping at 11.88 Gb/s and 11.88/1.001 Gb/s

* New Feature: Supports SMPTE ST 352: Payload ID packets

* New Feature: AXI4-Lite interface support

* Other: Initial release

SMPTE UHD-SDI TX (1.0)

* Version 1.0

* Initial release

SMPTE UHD-SDI TX SUBSYSTEM (1.0)

* Version 1.0

* New Feature: Supports SMPTE ST 259: SD-SDI at 270 Mb/s

* New Feature: Supports SMPTE ST 292: HD-SDI at 1.485 Gb/s and 1.485/1.001 Gb/s

* New Feature: Supports SMPTE ST 372: Dual Link HD-SDI

* New Feature: Supports SMPTE ST 424: 3G-SDI with data mapped by any ST 425-x mapping at 2.97 Gb/s and 2.97/1.001 Gb/s

* New Feature: Supports SMPTE ST 2081-1: 6G-SDI with data mapped by any ST 2081-x mapping at 5.94 Gb/s and 5.94/1.001 Gb/s

* New Feature: Supports SMPTE ST 2082-1: 12G-SDI with data mapped by any ST 2082-x mapping at 11.88 Gb/s and 11.88/1.001 Gb/s

* New Feature: Supports SMPTE ST 352: Payload ID packets

* New Feature: AXI4-Lite interface support

* Other: Initial release

SPI-4.2 (13.0)

* Version 13.0 (Rev. 11)

* Changed IP status to discontinued.

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 9)

* No changes

Sensor Demosaic (1.0)

* Version 1.0

* First version released

* Two interpolation methods optimize for sharper image detail or improved fringe tolerance

* Option horizontal filter to reduce zipper artifacts

* One, two, four, or eight pixel-wide AXI4-Stream video interface

* Video resolution support up to UHD at 60 fps

* 8, 10, 12, and 16 bits per component support

Serial RapidIO Gen2 (4.1)

* Version 4.1 (Rev. 1)

* General: Change in file calls during core generation. No affect on output files.

* Revision change in one or more subcores

SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 5)

* No changes

SmartConnect Node (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: Reset flop update for timing closure improvements in SLR designs.

SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 5)

* No changes

SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 4)

* No changes

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 10)

* Resolve CRITICAL WARNING:[Timing 38-282] Negative SETUP slack violation (7s75-fgga676). Also cleaned up the recommended pblocks for SEM controller for some 7 Series devices.

Switch Core Top (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

System Cache (4.0)

* Version 4.0 (Rev. 3)

* Bug Fix: Allow 64 bit Master AXI data width when only using generic AXI slave ports

* Bug Fix: Avoid losing transactions on AXI generic ports during arbitration

* Feature Enhancement: Added support for XPM memory

* Feature Enhancement: Improved AXI bus interface design rule checks

* Other: Added support for XA Zynq UltraScale+ and XA Spartan-7 devices

System ILA (1.1)

* Version 1.1

* The IP minor version has been changed to 1.1 due to changes in PC_status

* port width of Protocol checker

* Updated protocol checker version

* Revision change in one or more subcores

System Management Wizard (1.3)

* Version 1.3 (Rev. 6)

* General: Internal GUI Updates. No effect on the customer design.

TMR Comparator (1.0)

* Version 1.0 (Rev. 1)

* Feature Enhancement: Added input register to improve maximum frequency

* Feature Enhancement: Added additional bus interfaces

* Feature Enhancement: Support extended address for Trace interface

* Other: Production release

* Revision change in one or more subcores

TMR Inject (1.0)

* Version 1.0 (Rev. 1)

* Feature Enhancement: Improved LMB register access timing

* Feature Enhancement: Support extended address for LMB register interface

* Other: Production release

TMR Manager (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: Support VCU118 board in example design

* Feature Enhancement: Improved LMB register access timing

* Other: Production release

TMR Soft Error Mitigation Interface (1.0)

* Version 1.0 (Rev. 2)

* General: Production release

* General: Added support for XA Zynq UltraScale+ and XA Spartan-7 devices

* Revision change in one or more subcores

TMR Voter (1.0)

* Version 1.0 (Rev. 1)

* Feature Enhancement: Added parameter to enable Voter to be used to connect lockstep input bus interfaces

* Feature Enhancement: Added additional bus interfaces

* Feature Enhancement: Support extended address for Trace interface

* Other: Production release

TSN Tri Mode Ethernet MAC (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 9)

* Bug Fix: Fixed bug in Demo Test-Bench, for 2.5G, which wrongly flagged an frame check error during user injected error

* Revision change in one or more subcores

UHD-SDI GT (1.0)

* Version 1.0

* Initial release

UltraScale 100G Ethernet Subsystem (2.3)

* Version 2.3

* Port Change: Updated the s_axi_pm_tick port to pm_tick

* Port Change: Added rx_serdes_clk output port for the rs_fec enabled with shared logic in core config

* Feature Enhancement: Added AXI4-Lite support for AN/LT configuration

* Other: Support for streaming continuous packets instead of just a burst in example design

* Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)

* Version 4.4

* Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph

* Bug Fix: Fixed unsafe timing path between Sys_Clk and Pipe_Clk when RX EQ Auto Adapt is enabled

* Feature Enhancement: Enabled KCU1500 Xilinx Development Board

* Feature Enhancement: Removed tandem stage1/stage2 mux on the cfg_dsn input. This allows user to set this value as desired for stage1 and/or stage2 operation.

* Other: Enabled cfg_interrupt_msi_function_number port when MSI-X is enabled

* Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.7)

* Version 1.7 (Rev. 1)

* Feature Enhancement: Added new transceiver configuration preset options for GTY-3G_SDI/HD_SDI/HDMI

* Feature Enhancement: Added new transceiver configuration preset options for GTY-DisplayPort_5_4G/DisplayPort_2_7G/DisplayPort_1_62G

* Other: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides

* Other: Updated the choice of GTYE3/GTYE4 Reference clock sharing for line rates greater than 16.375 Gb/s

* Other: Added new XDC constraints conditionally for GTHE4 ES devices for handling additional timing constraints needed for DRP

* Other: Attribute update for PCIe Gen2/3 max capable designs for GTHE4 devices

* Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 5)

* Added support for XA Zynq UltraScale+ devices

* Added support for HBM UltraScale+ devices

* Updated and completed SSI Virtex UltraScale+ support; all features including classification, PEEK and diagnostic scan are implemented. Users should not use prior versions of this IP for deployment.

* Resolve (Xilinx Answer 68938) for the XCVU13P design not meeting timing with the maximum supported frequency of 125MHz

* Updated overlapping PBlocks to fix warnings in UltraScale VU190 and VU440 devices.

* When cap_rel is asserted while SEM controller is performing diagnostic scan, SEM controller prematurely deaaserts cap_req and the IP does not go to Idle until the scan completes.

UltraScale+ 100G Ethernet Subsystem (2.4)

* Version 2.4

* Port Change: Updated the s_axi_pm_tick port to pm_tick

* Feature Enhancement: Added TX OTN support for CAUI10 mode

* Feature Enhancement: Added AXI4-Lite support for AN/LT configuration

* Feature Enhancement: Added IP Integrator board support for VCU118 board

* Other: Support for streaming continuous packets instead of just a burst in example design

* Revision change in one or more subcores

UltraScale+ PCI Express 4c Integrated Block (1.0)

* Version 1.0

* Initial release

UltraScale+ PCI Express Integrated Block (1.3)

* Version 1.3

* Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph

* Bug Fix: Fix for Include GT Wizard in Example Design mode

* Feature Enhancement: Added option to enable external BUFG_GT/SYNC for sys_clk

* Feature Enhancement: Moved phy_clk module in support wrapper when selecting Include GT Wizard in Example Design mode

* Feature Enhancement: Added GT_COMMON sharing option

* Feature Enhancement: Added support to simulate tandem using the SIMULATION define. When this define is set, design_switch will be asserted and the core will operate as though stage2 is loaded.

* Feature Enhancement: Removed tandem stage1/stage2 mux on the cfg_dsn input. This allows user to set this value as desired for stage1 and/or stage2 operation.

* Feature Enhancement: Added support for xazu4ev and xazu5ev

* Revision change in one or more subcores

Universal Serial XGMII Ethernet Subsystem (1.0)

* Version 1.0

* General: New IP

Utility Reduced Logic (2.0)

* Version 2.0 (Rev. 3)

* No changes

Utility Vector Logic (2.0)

* Version 2.0 (Rev. 1)

* No changes

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 17)

* spartan7 automotive device support added

Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 8)

* New Feature: Added parameter ENABLE_420 to support YUV 420 video format; existing IP instances are unchanged

* Feature Enhancement: Added support for converting from any video format at the input to any video format at the output

* Revision change in one or more subcores

Video Deinterlacer (5.0)

* Version 5.0 (Rev. 8)

* Revision change in one or more subcores

Video Frame Buffer Read (2.0)

* Version 2.0

* Feature Enhancement: Added second buffer pointer for semi-planar formats

* Feature Enhancement: Added 64-bit address for memory mapped AXI4 interface

* Feature Enhancement: Added streaming formats RGBA and YUVA 4:4:4

* Feature Enhancement: Added memory formats RGBA8, BGRA8, BGRX8, YUVA8, and UYVY8

* Revision change in one or more subcores

Video Frame Buffer Write (2.0)

* Version 2.0

* Feature Enhancement: Added second buffer pointer for semi-planar formats

* Feature Enhancement: Added 64-bit address for memory mapped AXI4 interface

* Feature Enhancement: Added memory formats BGRX8 and UYVY8

* Revision change in one or more subcores

Video Horizontal Chroma Resampler (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

Video Horizontal Scaler (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 7)

* Bug Fix: Fixed problem with YUV420 remapping

* Other: Updated core to utilize XPM_FIFO

Video Letterbox Engine (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

Video Mixer (2.0)

* Version 2.0

* Feature Enhancement: Added second buffer pointer for semi-planar formats

* Feature Enhancement: Added 64-bit address for memory mapped AXI4 interface

* Feature Enhancement: Register map offsets re-ordered to handle both 32 and 64-bit addressing

* Feature Enhancement: Added UYVY8 and BGRX8 memory formats

* Feature Enhancement: Added per pixel alpha streaming formats RGBA and YUVA444

* Revision change in one or more subcores

Video On Screen Display (6.0)

* Version 6.0 (Rev. 14)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

Video PHY Controller (2.1)

* Version 2.1

* Bug Fix: Added interrupt for MMCM lock for TX and RX

* Bug Fix: Connected GTPOWERGOOD signal to register for GTHE4

* Bug Fix: Added TX reference clock Ready Invert support for HDMI

* Bug Fix: Corrected the CDC for CPLL Cal control registers

* Bug Fix: Removed DP protocol support for GTHE2

Video Processing Subsystem (2.0)

* Version 2.0 (Rev. 6)

* Feature Enhancement: Added format conversion to Color Space Conversion Only functionality (convert between RGB, YUV 4:4:4, YUV 4:2:2, and YUV 4:2:0)

* Revision change in one or more subcores

Video Test Pattern Generator (7.0)

* Version 7.0 (Rev. 8)

* General: Updated AXI Verification IP in Simulation Example Design

* Revision change in one or more subcores

Video Timing Controller (6.1)

* Version 6.1 (Rev. 11)

* Bug Fix: Fixed CDC handshaking problem for back-to-back AXI4-Lite transactions.

* Bug Fix: Fixed de-assertion of vblank to allow it to coincide with last pixel of the back-porch

Video Vertical Chroma Resampler (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

Video Vertical Scaler (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

Video to SDI TX Bridge (2.0)

* Version 2.0

* Use as hidden subcore for UHDSDI TX subsystem

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)

* Version 4.3

* Bug Fix: Updated arrow colors for JTAG debugger LTSSM graph

* Bug Fix: Update IP constraint file to remove invalid timing arch for asynchronous clocking mode

* Other: Enabled cfg_interrupt_msi_function_number port when MSI-X is enabled

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 8)

* Revision change in one or more subcores

XADC Wizard (3.3)

* Version 3.3 (Rev. 4)

* Bug Fix: Fixed range of ADC conversion rate

XAUI (12.3)

* Version 12.3 (Rev. 1)

* General: GTP Wizard settings update for RXLPM_BIAS_STARTUP_DISABLE for specific Artix devices

* Revision change in one or more subcores

XHMC (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 11)

* General: Comment change in C model. No change to functionality

* Revision change in one or more subcores

ZYNQ UltraScale+ VCU (1.0)

* Version 1.0

* No changes

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 6)

* DDR Pin Info support for following devices fixed.

* xc7z007sclg400,xc7z014sclg400,xc7z014sclg484,xc7z012sclg485

ZYNQ7 Processing System VIP (1.0)

* Version 1.0 (Rev. 2)

* Using interface versionless of package, interface and PC AXI VIP

Zynq UltraScale+ MPSoC (3.1)

* Version 3.1

* New features:

* 1. The fractional clocking enable (FracEn) option is provided in Vivado only for the DP_VIDEO and DP_AUDIO peripherals to facilitate their precise.

* clocking. When this option is checked/enabled the fractional value for the feedback value is configured for the respective PLL.

* 2.Load DDR Presets: This option loads factory provided presets. 

When these presets are loaded, all the DDR4 configurations will be loaded automatically. 

Each preset assumes a specific Memory Interface Device Frequency verify that the Actual Interface frequency is similar to the requested.

* Currently Xilinx provides three presets.

  • DDR4_KINGSTON_KVR21SE15S8: This configuration is for KINGSTON DDR4 part KVR21SE15S8/4.
  • DDR4_MICRON_MT40A256M16GE_083E: This configuration is for MICRON DDR4 part MT40A256M16GE 083E.
  • DDR4_SAMSUNG_K4A8G165WB_BCRC: This configuration is for SAMSUNG DDR4 part K4A8G165WB BCRC.

* Issues Resolved:

  1. SMMU register 0xFD5F0018 is always initialized with 0x8000001F as part of Erroneous initialization of IOU secure/non-secure access registers.
  2. Added parameter PSU_DDRC_ENABLE_LP4_HAS_ECC_COMP which will be enabled automatically when LPDDR4 ECC is enabled. user can still enable this parameter without ECC button enabled when testing a ECC board but with ECC disabled.
  3. Updated DDR4 tCK speed bin boundaries by 1ps to match DDR4 JEDEC specification.

  4. * 4.Corrected SD0 SD 2.0 over EMIO HDL wrapper bus width to 4-bit wide.

  5. * 5.USB2.0 works now independently of USB3.0 GTR.

  6. * 6.Fine granularity refresh mode = 1X is now allowed only in Temp Controlled Refresh Mode PS DDR Temp Controlled refresh requires 1x refresh mode.

  7. * 7.The default PS to PL AXI interface width changed: LPD is 32-bit while both HPDs are 128-bit.

  8. * 8.DDR4-2400T speed bin added.

axi_msg (1.0)

* Version 1.0

* General: New IP

axi_sg (4.1)

* Version 4.1 (Rev. 7)

* AXI SG uses XPM FIFO

* Revision change in one or more subcores

interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes

lib_bmg (1.0)

* Version 1.0 (Rev. 9)

* uses XPM memories

lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 9)

* RTL wrappers updated to use xpm_fifo

lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes

AR# 69903
Date 10/17/2017
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2017.3
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