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AR# 7013

14.x Timing - The maximum delay path does not match the minimum period value in any timing report (two-phase)

Description

When I examine a timing report, the reported maximum delay path is less than the minimum period (by definition, the maximum delay path should be the same as the minimum period). I have instructed the software to keep the longest five path delays.

Solution

Check your design to see if any two-phase clocks are present, as these will affect the delay. For example, if the period is 50 ns, the total delay will be 50 ns x 2 = 100 ns to account for the two-phase clock in the design.

Consequently, if the highest reported delay is 75 ns, you must report more than just five delays in order to see the two-phase clock at 50 ns, as delays are reported in order from longest to smallest.

Also, if related clocks are used, the minimum period can be based upon a cross-clock domain path. To see the actual minimum period, run an Auto-Generated Path Report from Timing Analyzer or TRACE.

For more information, see (Xilinx Answer 4313) and (Xilinx Answer 6501).
AR# 7013
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
  • Less