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AR# 70165

2017.3 Vivado IP Flows - Synthesizing an Ethernet subsystem IP gives ERROR: [Designutils 20-176] Cannot open XDC file "*_board.xdc"


In Vivado 2017.3, I am seeing the following error related to a board XDC file that is not getting generated. 

However, Vivado seems to think that the IP core is up-to-date until synthesis is run.

There is an error when synthesizing the IP core when using either OOC generation mode or as part of the complete design.

For example: 

When synthesizing a design with an Ethernet Subsystem IP core, an error occurs related to a missing board.xdc file.

[Designutils 20-176] Cannot open XDC file "c:/project_name/project_name.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_929b_mac_0_board.xdc

Resetting and regenerating the output products does not resolve the issue.

If the project is closed and reopened, there is a list of files that are not found related to the IP core.


A problem was found in Vivado 2017.3 where not all files of Hierarchical IP (HIP) are being generated when there is a hardware evaluation license for the IP in use.

During generation, the files are considered delivered but will not be found by Vivado.

When using a Full license all of the files are delivered correctly.

This issue will be fixed in Vivado 2017.4.

To work around the issue in Vivado 2017.3, set the following parameter in the Vivado Tcl console and then reset and regenerate the Output Products for the Block Diagram.

set_param ips.generation.cacheXitResults false

A tactical patch which fixes this issue in Vivado 2017.3 is available in (Xilinx Answer 70182).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
68924 2017 Vivado IP Flows - Known Issues for Vivado 2017.x IP Flows N/A N/A
AR# 70165
Date 11/29/2017
Status Active
Type Known Issues
  • Vivado Design Suite - 2017.3
  • Vivado Design Suite - 2017.3.1
  • Ethernet
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