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AR# 7090

CORE Generator - An alternate method for COREGen VHDL model instantiation in a multi-level/hierarchical design

Description

Keywords: core, VHDL, behavior, simulation

Urgency: Standard

General Description:
This Answer Record illustrates an alternate method for instantiating a CORE Generator VHDL model in a multi-level design using the CORE Generator flow. With this method, all of the instantiation information is bundled into a single top-level configuration. (The better coding practice is to create a VHDL configuration at every level of hierarchy.)

Solution

For multi-level designs, the recommended coding practice is to declare a VHDL configuration at every level of your design hierarchy when instantiating a module deep in a design that consists of multiple levels. Declaring a configuration at each level allows you to delay the binding of a specific instance to a specific library entity/architecture pair until the end stages of compilation.

Although this approach is preferred practice because of readability and ease of maintenance, it is also possible to encapsulate all of the information in a single, top-level configuration.

For example, suppose you have a top-level design called "top" that has an architecture called "struct_top". Instanced in this architecture is a component called "comp_1", which is an interface to the entity "ent_1"; this, in turn, has an architecture called "struct_1". Inside struct_1 is one or more instance(s) of the component "comp_2", which is a CORE Generator C_MUX_BIT_V1_0.

Top level design

entity top
...
architecture struct_top of top is
...
end

entity ent_1
...
architecture struct_1 of ent_1 is
...comp_2
end

component comp_1

To make sure that the behavioral model of the CORE Generator module is found, you need the following as your top-level configuration:

configuration top_cfg of top is
for struct_top:
for all : comp_1
for struct_1: architecture of comp_1

NOTE: The following is the snippet from the .vho file:

Start cut
for all: comp_2
use entity XilinxCoreLib.C_MUX_BIT_V1_0(behavioral)
generic map(etc etc);
end for;

End cut

end for;
end for;
end for;
end configuration;

This is a recursive construction; you can use this as far down the hierarchy as you wish.
AR# 7090
Date Created 07/23/1999
Last Updated 10/09/2003
Status Archive
Type General Article