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AR# 7105

Mentor: pld_edif2tim gives Error: Unable to resolve reference "my_bus_7_0_" of type "portRef"


Keywords: edif2tim, Mentor, ngdanno, ENRead, timing simulation, ngd2edif

Urgency: Standard

General Description:

Using the Xilinx/Mentor interface I am running pld_edif2tim on my design.edn
that has come from the xilinx tool (ngd2edif), and I get the following error in
the transcript window:

// Note: Reading EDIF file "/home/testcase/top.edn" (from: Synthesis/EDIF
Interface/Command Interface 85)
// Error: Unable to resolve reference "my_bus_7_0_" of type "portRef".
(from: Synthesis/EDIF Interface/System 04)
// Error: Can NOT create a design. Was NOT able to read the edif file successfully.
(from: Synthesis/EDIF Interface/Command Interface 1C)

I have an EDIF macro in my top level schematic design, for which the EDIF was
created using Synplicity.

What can I do to get around this to do a timing simulation?


Currently the only way to get around this is to de-select the simulation
option "correlate simulation data to input design" which will NOT use
the NGM file in NGDAnno. The drawback to this is you will not be
able to cross-probe back to the original design.

Development is currently looking into this.
AR# 7105
Date Created 08/31/2007
Last Updated 10/03/2008
Status Archive
Type General Article