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AR# 7112

Configuration - Is the D0 pin the MSB or LSB? What is the byte-swapping option for PROM file generation (MCS/EXO/TEK)?


General Description:

Application Notes (Xilinx XAPP138): "Virtex FPGA Series Configuration and Readback" and (Xilinx XAPP151): "Virtex Configuration Architecture User Guide" state that the D0 pin is MSB during configuration. Is the D0 pin MSB or LSB during configuration? Is this different from other FPGA families, such as the XC4000/XC3000 families?

Also, what is byte-swapping?


The D0 pin corresponds to the LSB of each byte when the MCS, EXO, TEK, or default HEX file is generated in the PROM File Formatter (this is referred to as a "byte-swapped" file). The default for the HEX file is to Swap Bits; however, you can deselect this for HEX files. When you deselect this option, the D0 pin then corresponds to the MSB of each byte (i.e., this becomes a non byte-swapped file).

The ".bit" and ".rbt" files produced by BitGen are not byte-swapped.

This is true for all FPGA parallel modes, including Express, Synchronous/Asynchronous Peripheral, Master/Slave Parallel, and SelectMAP.


Xilinx software creates byte-swapped files because of the general convention of bus ordering. Generally, when bytes are used, the left-most bit (MSB) corresponds to the highest number in the bus (D0). For Xilinx configuration hardware, the most significant bit of each byte corresponds to D0, not D7. If a processor or logic device is being used, that hardware would usually need to compensate for this deviation from convention. Byte-swapped files are created so that logic devices such as processors (and other FPGAs) can place the left-most bit of each byte on D0 when configuring.

If a ".bit" or ".rbt" or non byte-swapped HEX file is used for parallel download, the MSB on the processor must be routed to D0 on the FPGA.

AR# 7112
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article