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AR# 7149

V2.1i COREGEN, C_IP1: Known Issues in the C_IP1 Cores update


Keywords: coregen, c_ip1, update, issue, foundation, viewlogic, verilog, vhdl

Urgency: standard

General Description:
Known Issues in the C_IP1 Cores update


Foundation Flow:
1. (Xilinx Solution 7151): V2.1i COREGEN, C_IP1, VIRTEX,
FOUNDATION: Line 3: Wrong number of fields BUS" / Foundation
integration problem for Virtex BaseBLOX modules with 1-bit wide input

Viewlogic Flow:
1. (Xilinx Solution 7143): V2.1i COREGEN, VIEWLOGIC: "ERROR:
cleanUpSymbolFile: Could not read symbol file: <project_directory>\sym\<modulename>.1"

Verilog and VHDL behavioral simulation:
1. (Xilinx Solution 7148): V2.1i COREGEN, VIRTEX: Problems with SCLR and
SINIT synchronous control signal behavioral modelling in the LD-Based LATCH

AR# 7149
Date Created 07/30/1999
Last Updated 08/01/2001
Status Archive
Type General Article