We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7160

FPGA Compiler, FPGA Express: What netlist formats are supported for Xilinx devices?


Keywords: FPGA, Compiler, 1999.05, netlist, edif, xnf, Express

Urgency: Standard

General Description:
What format netlist must I produce when using Synopsys products? What choices do I have?


Virtex designs require EDIF netlists; XNF is not supported. When using FPGA Compiler
or Design Compiler, only generate a .SEDIF file. FPGA Express / Compiler II will produce
a .EDF file.

For non-Virtex devices (3k, 4k, 5k, Spartan, 9k), Design Compiler will produce EDIF (.SEDIF)
only, and FPGA Compiler will produce XNF (.SXNF) only. FPGA Express / Compiler II will
produce XNF files for these families, but will produce EDIF in a future release
(version 3.4).
AR# 7160
Date Created 08/02/1999
Last Updated 08/11/2003
Status Archive
Type General Article