We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7233

ngd2edif: What's the bus designator in the edif file produced by ngd2edif, and why is it buses don't have the designator when ngdanno run with the .ngm file


Keywords: ngd2edif, Bus, Desiganator

Urgency: Standard

Problem Description:

The edif file produced by ngd2edif contains designators on single bit Input or Output
port, such as the following:
(port shout
(direction OUTPUT)
(designator "223")

However, if the Input or Output are buses, the designator may not show up for
the bus ports in the edif file.

What does the designator mean? and why is it the buses sometimes don't have
the designator definition in the edif file produced by ngd2edif?


The designator indicates the pin location of the Input or Output port. The above
example shows that Output port shout is on P223.

For bus ports, the logical back annotation, which is the annotation running with ngm
file (ngdanno <design>.ncd <design>.ngm), the designators will not be written in the
edif file, because the EDIF itself does not provide a way to specify a designator for
each member of the port array.

In physical back annotation, which is the annotation running without ngm file
(ngdanno <design.ncd>), the bus port is reconstructed, and the designators will
be attached to each bus port.
AR# 7233
Date Created 09/01/2007
Last Updated 06/13/2002
Status Archive