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AR# 7237

V2.1i COREGEN, Virtex, Foundation - Invalid EDIF with shorted nets produced for Virtex Dual- and Single-Port Block memory on first iteration.


Keywords: block, RAM, memory, core, EDIF, EDN, Virtex

Urgency: Hot

General Description:
After starting up a CORE Generator session, if either a Virtex Dual-Port or Single-Port
Block Memory is the first core that is generated, the EDIF implementation netlist may
be invalid. In some cases, there may be nets that are shorted together. For example,
an address bit may be shorted with the CLK signal:

(net (rename N3 "addr<1>")
(portRef addr_1_)
(portRef ADDRA_1_ (instanceRef BU0))
(portRef ADDRB_1_ (instanceRef BU0))
) (net (rename N2 "clk")
(portRef clk)
(portRef CLKA (instanceRef BU0))
(portRef CLKB (instanceRef BU0))
(net (rename N2 "addr<0>")
(portRef addr_0_)
(portRef ADDRA_0_ (instanceRef BU0))
(portRef ADDRB_0_ (instanceRef BU0))

In the snippet above, addr<0> and CLK are shorted together because they were both
renamed to "N2". This can cause "duplicate net" errors when simulating a design
containing such a core in Foundation.



** This problem was fixed in Service Pack 2 for the 2.1i release. **

Previously suggested work-around (provided for reference only):

The problem is only seen when the core is generated in GUI mode; when the core is
generated in batch mode, this problem does not occur.

To regenerate the core in batch mode, read in the .XCO file by going to File->Execute
Command File, and specifying the .XCO file as input.



The problem has been only seen when you generate a Dual Port or Single Port
Virtex Block RAM immediately after starting up the CORE Generator.
You must regenerate the respective core a second time within the same
session to get a valid EDIF netlist.
AR# 7237
Date 04/11/2001
Status Archive
Type General Article