We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7262

FPGA Express: Is there an option to disable carry logic?


Keywords: FPGA Express, Foundation, VHDL, Verilog, carry, arithmetic

Urgency: Standard

General Description:
Is there an option to disable carry logic when synthesizing HDL for XC4000, Spartan
and Virtex architectures?


There is no way to disable the inference of carry logic when synthesizing arithmetic
functions using FPGA Express. As long as arithmetic operators are used in your HDL
code, carry logic will be inferred.
AR# 7262
Date Created 08/31/2007
Last Updated 10/03/2008
Status Archive
Type General Article