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AR# 7382

FPGA Express 3.2: Synopsys Internal Error, Abort at 219


Keywords: Synopsys, FPGA Express 3.2, Internal, error, Foundation

Urgency: HOT

When synthesizing a design with FPGA Express, the following error may occur:

"Abort at 219" or "Abort at 217"


These particular errors are typically due to out of memory issues. If the design has multiple
HDL modules, compile each separately to see if one in particular causes the problem.

Often, the cause is a looping construct within the HDL source. If a design contains
nested or complex FOR loops or GENERATE statements, expand these constructs
manually and resynthesize.

Synopsys expects to resolve these memory issues with the next full release of FPGA
Express, version 4.0.
AR# 7382
Date Created 08/26/1999
Last Updated 08/11/2003
Status Archive
Type General Article