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AR# 7433

2.1i COREGEN, ACTIVE-VHDL - Issues related to compiling CORE Generator 2.1i VHDL models for the Active HDL simulator


Keywords: compile, VHDL, core, active

Urgency: Standard

General Description:
What issues are there regarding the compiling of CORE Generator 2.1i VHDL models
for the Active HDL simulator?

This solution contains some tips on compiling the CORE Generator VHDL library for
Active VHDL. For the latest information, please contact support@aldec.com directly.


1. The first issue is associated with a reference to an MTI-specific "arithmetic" library
in CORE Generator 2.1i models. The work-around is to alter the prims_sim_arch.vhd
file, as described in (Xilinx Solution 6771).

2. The second issue is an Active HDL problem, which is flagged by the following
error message:

Error: COMP96_0149: pdafirvht.vhd : (263, 54): Explicit type conversions are allowed
between closely related types only.

The offending line

filter_coefficients := filter_coefficients_type(coefficients(0 TO number_of_taps-1));

should be replaced by

FOR i IN 0 TO number_of_taps-1 LOOP
filter_coefficients(i) := coefficients(i);

3. Although Active HDL claims to support MTI compile syntax, it does not support
wild cards in the arguments to the VCOM command. To compile the CORE Generator
VHDL models, you must specify the name of each VHDL model individually if you are
trying to use an MTI syntax compile script.
AR# 7433
Date Created 09/01/1999
Last Updated 09/03/2001
Status Archive
Type General Article