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AR# 7569

XPLA ISP Programmer - "Warning: Cannot find ISP Cable/Board or loose connect!"

Description

Keywords: XPLA, PC-ISP, programmer, ISP, ISC, JTAG, CoolRunner, error, warning, loose, connect, board, cable

Urgency: Hot

General Description:
When using XPLA Programmer software, I encounter the following warning:

"Warning: Cannot find ISP Cable/Board or loose connect!"

How do I fix this?

Solution

1

If the software does not work with a board that is known to be good (ISP Demo board or some other ISP board), or if this is a first time installation, please verify the following:

(NOTE: If the software works with another ISP target board, skip to Item 8.)

1. Verify that the latest version of the ISP software has been installed. This is available on the Xilinx CoolRunner web site at:
http://www.xilinx.com/products/software/webpowered.htm.

2. ISP software must be installed using a directory structure of eight or fewer characters. Do not use any spaces.

3. Software is supported under Windows 95 and Windows NT only. (The software has not been verified to run under Windows 98.) ISP software above version 4.00 is not supported by Windows 3.1 or Windows 3.11.

4. If the software is installed under Windows NT, the installer must have administrator privileges, and the software must be installed locally (not on a server).

5. Software should be installed on an OS with no other applications running in the background. Installing while Microsoft Office is running has proven to create conflicts.

6. Please ensure that you are using a CoolRunner download cable, a ByteBlaster Cable, or a Xilinx Download cable. If you are using a custom cable, please see (Xilinx Answer 7570). There may NOT be a dongle between the parallel port and the cable.

7. Once the tool has been started, please verify the following:

--- From the front GUI, select the "Port Setup" pull-down menu. Verify that the "Select PC Parallel Port" selection is in the "Auto" mode. Verify that the correct cable type (Xilinx/CoolRunner/Altera) has been selected. If you have more than one parallel port, please see Resolution 2.

--- From the main GUI, select the "Help" pull-down menu. Under "Output/Debug Options," verify that all checkboxes are clear.

8. An incorrect document detailing the pin out of the JTAG header was placed on the Xilinx web site. The correct pin list is in the online help of the tool (Help -> Contents -> Hardware -> Download Cable).

-- Verify that the pin out of the JTAG header is as follows:

TCK: pin 2
TMS: pin 4
TDI: pin 6
TDO: pin 8
GND: pins 1, 3, 5, 7
N.C.: pins 9, 10

9. If you are using the CoolRunner Download cable and a JTAG chain configuration, verify that the first part in the JTAG chain is a CoolRunner. The passive CoolRunner download cable may not drive other vendors' JTAG parts.

10. For a JTAG chain, verify that TDO of Device 1 is attached to TDI of Device 2, and so forth. Ensure that the TMS and TCK pins are connected parallel to the TMS and TCK of other parts in the chain.

11. We recommend that all JTAG signals be terminated with 10k pull-up resistors.

12. If you are using a passive cable, we recommend that no more than 5 devices be placed in a JTAG chain without board I/O (JTAG signal) buffering. It is always a good practice to buffer all board I/O signals.

13. Please check continuity with the cable attached to the board by checking the signal path from the DB25 connector directly to the ISP pins on the components. There should be an approximate 100 Ohm resistance from the DB25 pins to the I.C. pins for the CoolRunner Download Cable. The pin numbers for the DB25 pins are:

TCK: pin 2
TMS: pin 4
TDI: pin 3
TDO: pin 11
GND: pins 18, 19, 20, 21

14. Test the design to see if it will work with a device that is programmed externally to the system.

15. Ensure that power and ground are connected to the proper pins. Also, verify that the system has power applied.

16. Verify that the device is "de-coupled" from the appropriate capacitors.

17. Verify that the system in which the CPLD is installed is not trying to operate or access the ISP device while ISP operations are in progress.

18. Verify that JTAG traces have continuity to the correct parts in the chain and that incorrect connections (such as solder bridge shorts) are unlikely.

19. Verify that the components do not have mixed voltage inputs. (NOTE: Exceptions are "AS" parts and the XCR3320 parts, which are 5V-tolerant.)

2

If you have more than one parallel port, the cable may not be auto-detected. In this situation, please manually select each port until the cable is detected.

3

The XPLA3 (and certain older XPLA1 Enhanced devices) supports the use of JTAG pins as I/O. In this situation, a device will program initially, but will not respond to JTAG instructions (and the ISP Programmer) afterwards, because the JTAG pins are in user mode.

In order to re-activate the ISP capability of the CoolRunner device, pull the Port_Enable pin to 3.3V. This will re-enable the ISP functionality of the JTAG pins.

When the ISP pins are needed for standard I/O, the Port_Enable pin may be pulled down (or connected directly to) Ground.

For more information on XPLA3 and ISP, please see (Xilinx XAPP343): "In-System Programming of XPLA3 Devices."
AR# 7569
Date Created 09/15/1999
Last Updated 08/29/2002
Status Archive
Type General Article