We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7575

XPLA Programmer - What should the ATE vector clock speed for TCK be?


Keywords: XPLA, PC-ISP, programmer, ISP, ISC, JTAG, CoolRunner,
ATE, TCK, clock, speed, vectors

Urgency: Standard

General Description:
What clock speed should be used to run ATE vectors?


We generate our program and init pulses by requesting a delay that is based
upon a number of TCKs during programming. This value is set at an arbitrary
10,000 clock pulses (for at least a 10ms delay). Our devices require a 10 ms
program pulse; therefore, TCK generated by the ATE setup can not be faster
than 1 MHz.
AR# 7575
Date Created 09/15/1999
Last Updated 08/31/2001
Status Archive
Type General Article