We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7602

CPLD CoolRunner-II/XPLA3 - CoolRunner parts are drawing too much current (power)


Why are my CoolRunner parts drawing so much current?


The following is a list of common problems that cause high current:

- I/O or bus contention.

- Unused I/O pins must be terminated to prevent floating voltages, which put transistors into the linear region.

- Clock networks present a large capacitance load internally. You should use global clocks only if more than 25% of the registers are being clocked by that clock, or if necessary to meet timing.

- Ensure that I/O pins are as close to either the Ground or VCCIO rails as possible; failure to do so increases leakage current.

- Power-up current surge requirements must be met. This information can be found in the applicable device data sheet as a note under Tconfig (configuration time).

- Avoid unnecessary use of ISP operations such as Erase/Program/Verify because they require extra current.

- CoolRunner-II only: If unused I/O pins are connected to active signals, this will cause extra power consumption. Save power by enabling these I/O as inputs and enabling DataGate on them.

- XPLA3 only: Global clock pins are input only, and do not have internal pull-ups; these pins should be terminated if not used.

AR# 7602
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article