What are the DC switching levels of the JTAG inputs for Virtex/-E and Spartan-II/-IIE devices?
JTAG Input Pins
The JTAG input pins (TDI, TMS, TCK) are dedicated and do not reside in any banks. They are powered by VCCINT and are not affected by VCCO or any other power plane. The pins are designed as LVTTL, and when they are actively driven, they must be driven to LVTTL levels. The pins have internal weak pull-ups to VCCINT, and this voltage level holds the lines in a logical High state. If external pull-ups are used on the board, the pull-ups can be tied to the VCCINT voltage level.
JTAG Output Pins
The TDO pin is in Bank 2 and is powered by the VCCO pin in Bank 2. The TDO pin always drives rail-to-rail between Ground and the voltage level on VCCO in Bank 2.
Related Answer Records
- For information on the TDO output voltage levels, see (Xilinx Answer 8522).
- For information on I/O switching levels during Boundary Scan testing (EXTEST), see (Xilinx Answer 8762).
- For information on IBIS simulations for JTAG pins, see (Xilinx Answer 12085).