We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7816

Virtex CLKDLL- Two CLKDLLs cascaded together cause the output of the second CLKDLL to be invalid


When I cascade two CLKDLLs together with the Lock signal of the first CLKDLL driving the RST of the second CLKDLL, the second CLKDLL never locks, and its outputs do not have the correct clock frequencies. This issue happens on the board after the design is downloaded, and the functional/timing simulation did not exhibit this problem.


To work around this problem, insert an SRL16 and an inverter between the LOCKED and RST pin of the first and second CLKDLL.

For more information, please see (Xilinx XAPP132): "Using the Virtex Delay-Locked Loop."

AR# 7816
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article