We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7887

4.1i NGD2VHDL, NGD2VER, SIMPRIMS - False setup violation occurs on X_FF instance immediately after time 0. (VHDL, Verilog)


Keywords: SimPrim, Verilog, setup, violation, SDF

Urgency: Standard

General Description:
A setup violation occurs immediately after the start of initialization because the settling of initialization values progates longer than the allowed setup of the flip-flop.


This is a false setup, reported because of time zero startup. It can be safely ignored because the global reset signal is pulsed to re-initialize the FFs.

To resolve the issue, consider delaying clock until the global reset signal is pulsed. For example, consider the XC4000E case:

`define GSR_PULSE 100
`define CLK_PER 200

initial begin
clk = 0;
// Wait till GSR is finished, then cycle clock
#`GSR_PULSE forever #(`CLK_PER/2) clk = ~clk;

reg GSR;
assign glbl.GSR = GSR;
reg GTS;
assign glbl.GTS = GTS;

initial begin
GSR = 1; GTS = 1;
// GSR is finished
#`GSR_PULSE GSR = 0; GTS = 0;

Please see (Xilinx Answer 5009) for information on how to drive the global signals.
AR# 7887
Date 06/13/2002
Status Archive
Type ??????
Page Bookmarked