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AR# 7895

2.1i COREGEN, C_IP3: Known Issues in the C_IP3 IP Update


Keywords: coregen, c_IP3, ip, known, adder, addsub, subtractor, accumulator, distributed memory,
distributed ram, virtex, counter, comparator

Urgency: hot

General Description:
C_IP3 IP Update Known Issues:


VHDL Simulation Analyze Order:
(Xilinx Solution #6250) has been updated to indicate the order in which
the VHDL behavioral simulation models must be analyzed for this



1. 2.1i COREGEN, C_IP2, UNIX: "Shrink method not supported" / "ERROR: Could not load/define class file xxxxxx" / "ERROR locating library for class xxxx" when setting Register Options. Please refer
to (Xilinx Solution #7711).

2. 2.1i COREGEN, C_IP1, C_IP2, C_IP3: Version of generated module does not match version
number in the corresponding datasheet. Please refer to (Xilinx Solution #7578).

Distributed Memory Core:

1. 2.1i COREGEN, C_IP3: MAP: "ERROR:xvkpu - Unable to obey design constraints" / Distributed Memory Cores may fail in MAP. Please refer to (Xilinx Solution #7906).

2. 2.1i COREGEN, C_IP3: How to specify default initialization values other than "0" using the MIF
file. Please refer to (Xilinx Solution #7896).

3. 2.1i COREGEN, C_IP3, Distributed Memory: Customization GUI does not indicate what legal data width and depth ranges are. Please refer to (Xilinx Solution #7924).

Binary Counter Core:

1. 2.1i COREGEN, C_IP3: Error in COUNTER HDL behavioral model when COUNT BY VARIABLE and COUNT TO
VALUE = "MAX" are selected. Please refer to (Xilinx Solution #7897)

2. 2.1i COREGEN, C_IP3: Synchronous INITcontrol does not work when "Restrict Count" option is selected for
Virtex Binary Counter. Please refer to (Xilinx Solution #8153).

In addition, the known issues documented for the C_IP1 and C_IP2 releases still apply, as
documented in (Xilinx Solution #7149) and (Xilinx Solution #7395), respectively.
AR# 7895
Date Created 10/20/1999
Last Updated 08/24/2001
Status Archive
Type General Article