UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8007

Virtex CLKDLL - Why is the output jitter specification in the data sheet less than the cycle-to-cycle input jitter?

Description

The data sheet indicates that the cycle-to-cycle input jitter is +/-300 ps, but that the output cycle-to-cycle jitter is +/-60 ps. How is it possible that the output jitter is shorter than the input jitter?

Solution

The DLL output jitter and skew specifications do not include input clock jitter. Because input clock jitter can vary considerably between applications, input jitter is not included in the DLL output specs. Consequently, the DLL output jitter spec of +/-60 ps is the amount of jitter that the DLL can add to the existing input clock jitter.

Remember that the DLL is a delay line, not a clock generator (like a PLL), so a clean input clock will lead to a clean output clock, and a flawed input clock will lead to a flawed output clock (with the exception that the input clock can be duty-cycle corrected).

The DLL output cycle-to-cycle jitter of +/-60 ps is based on CLKDLL tap adjustment. Other factors such as input jitter, internal DLL delay, and routing also contribute to the resulting cycle-to-cycle jitter. See (Xilinx Answer 13397) for more information on cycle-to-cycle jitter.

For timing budgeting, use the period jitter. See (Xilinx Answer 13645) for more information.

AR# 8007
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article