UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8064

2.1i COREGEN: Outputs in Dynamic Constant Coefficient Multiplier Verilog model change asynchronously

Description

Keywords: verilog, constant, coefficient, multiplier, latency

Urgency: standard

General Description:
The following problems may be seen with the Verilog model for the 4K Constant Coefficient
Multiplier core when simulating in Synopsys VCS or Verilog-XL:

1. There is no latency between the input transitions and output transitions--the output
changes immediately after a new input value is clocked in.
2. Race condition associated with transitioning of the output on a rising clock edge

The problems are similar to those found in the Virtex Dynamic Constant Coefficient Multiplier Verilog model
as described in (Xilinx Solution #8020). The symptoms show up in VCS and Verilog-XL.

Solution

1

Under investigation.

2

An alternative workaround is to generate a post-NGDBUILD simulation netlist for the
core in place of its behavioral model. Please refer to (Xilinx Solution #8065) for details on
how to do this.
AR# 8064
Date Created 11/15/1999
Last Updated 08/01/2001
Status Archive
Type General Article