AR #8066 - ModelSim (SE, PE) - How do I compile the XilinxCoreLib (CORE Generator) libraries?
ModelSim (SE, PE) - How do I compile the XilinxCoreLib (CORE Generator) libraries?
| AR# | 8066 |
| Topic | SW-3rd Party Sim Tool |
| Last Modified | 2008-08-18 00:00:00.0 |
| Status | Archive |
Description
Keywords: ModelSim, Verilog, MTI, CORE Generator, COREGen, vlog, XilinxCoreLib, compile, VHDL, vcom
Urgency: Standard
General Description:
How do I compile the XilinxCoreLib (CORE Generator) libraries for ModelSim?
Solution
For the Xilinx 4.1i/4.2i software:A TCL script (available on the Xilinx FTP site) works with the EE/SE/PE versions of ModelSim.
PC:
ftp://ftp.xilinx.com/pub/swhelp/mti/xilinx_lib_4.zip
UNIX:
ftp://ftp.xilinx.com/pub/swhelp/mti/xilinx_lib_4.tar.gz
For 5.1i and above use Compxlib.
COMPXLIB is a tool for compiling the Xilinx HDL-based simulation libraries with the tools provided by simulator vendors. Libraries are generally compiled or recompiled anytime a new version of a simulator is installed, a new ISE version is installed, a new service pack is installed, or when a new IP Update is installed.
Before starting the functional simulation of your design, you must compile the Xilinx simulation libraries for the target vendor simulator. For this purpose, Xilinx provides COMPXLIB.
Note: Do NOT use with ModelSim XE (Xilinx Edition) or ISE Simulator. These simulators come with precompiled Xilinx libraries.