We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 8261: 2.1i COREGEN, VIRTEX, FFT, C_IP4: "WARNING: Core vfft16 did not generate product VerilogSim."
2.1i COREGEN, VIRTEX, FFT, C_IP4: "WARNING: Core vfft16 did not generate product VerilogSim."
Keywords: virtex, FFT, verilog, verilogsim
General Description: After selecting "Verilog" as one of the Behavioral Simulation options in the Project Options menu, and then trying to generate a Virtex FFT core from the C_IP4 release, you may see the following warning:
"WARNING: Core vfft16 did not generate product VerilogSim."
The warning means that the core did not generate a Verilog behavioral model.
In the C_IP4 release, there is no Verilog behavioral simulation support--only a .VEO template is generated. Verilog behavioral simulation support will be added to the cores in a future release scheduled for 3Q00.
As a workaround, you may generate a post-NGDBUILD gate level netlist for the module and use it for your pre-implementation verification. The procedure for generating a post-NGDBUILD simulation netlist is described in (Xilinx Solution #8065).