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AR# 8263

Virtex CLKDLL VHDL Simulation - DLL outputs are not toggling (no output); CLKIN is delayed


Keywords: CLK0, CLK2X, output, stuck, no switching, DLL, SimPrim

Urgency: Standard

General Description:
I am using the CLKDLL and performing a VHDL back-end timing simulation using the Xilinx 2.1i tools. The CLKIN to the DLL is delayed for hundreds of nanoseconds, or has a signal that is much slower than the specified frequency range for the DLL by hundreds of nanoseconds. After this period of time, CLKIN changes to a frequency within the range of the DLL, but the outputs are delayed. Also, the outputs, such as CLK0 and CLK2X, are not toggling.


This is a SimPrim CLKDLL model problem. The model is delayed in a "wait" statement when the CLKIN pin is stimulated as described. You can "comment out" the following line (line 1841) in the simprim_VITAL.vhd file:


This will be fixed in the next major release of the Xilinx software.
AR# 8263
Date Created 08/31/2007
Last Updated 08/25/2003
Status Archive