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AR# 8369

3.1i XST - What types of Generate Blocks are supported in VHDL?

Description


General Description:

What types of Generate Blocks are supported in VHDL?



(NOTE: The constructs reported below are supported in the 4.1i software release.)

Solution


Structural Generate:



This is supported by XST.



This is a concurrent statement that is replicated to produce multiple concurrent statements.



architecture block of register is

-- signal and component declarations

begin

cell_array : for bit_index in 0 to 10 generate

signal data : std_logic;

cell_storage : D_flipflop

port map (clk=>clock, d=>data_in(bit_index),

q=>data_unbuffered);

cell_buffer : tristate_buffer

port map (a=>data_unbuffered, en=>out_enable,

y=>data_out(bit_index);

end generate cell_array;

end architecture block;



VHDL supports two types of Generate Blocks, Structural and Process.



Process used in Generate:



This is not supported by XST.



The signals "ifetch_freq", "write_freq", and "read_freq", and the process "access_monitor" are only included in the design if the generic constant instrumented is true.



entity computer is

generic (instrumented : boolean :=false);

port (....);

end entity computer;



architecture block of computer is

-- signal and component declarations

begin

instrumentation : if instrumented generate

signal ifetch_freq, write_freq, read_freq : real := 0.0;

begin

access_monitor : process is

begin

-- body of process statement

end process access_monitor;

end generate instrumentation;

end architecture block_level;
AR# 8369
Date Created 08/31/2007
Last Updated 01/19/2012
Status Archive
Type General Article