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AR# 8398

2.1i Foundation Logic Simulator -Timing simulation of Virtex DLL fails when the input frequency is higher than 100MHz

Description

Keywords: FNDTN, Virtex, CLKDLL, timing, simulation

Urgency: Hot

General Description:
When I perform a timing simulation of a Virtex CLKDLL, the CLKDLL functions properly to a specified clock frequency, then fails to output
the correct (or any) frequency.

Solution

This result is caused by lump sum modeling. This issue may be resolved in two ways:

1. Use a simulator that supports transport or transparent switches. This permits the small clock pulses to pass through the logic, which allows the CLKDLL to simulate correctly.

2. Set the environment variable "XIL_PP_OPTIMIZE" to true:

set XIL_PP_OPTIMIZE=1;

Then, regenerate the timing simulation files.
AR# 8398
Date Created 01/11/2000
Last Updated 09/17/2002
Status Archive
Type General Article